A Look at Material Advancements, Novel Process Development and Dealing with Defects

March 27, 2015

April 14, 2015 – The abstract of a paper recently presented at SMTA Dallas by Universal Instruments’ Advanced Process Lab.

The trend in packaging technologies that enables faster, more effective data transfer, and processing is a continuous goal for the entire supply chain. We look to understand how this continuous decrease in the size of components brings new reliability challenges as the micro-structure of lead-free solder alloys is significantly affected by solder volume.

It is well known that the micro-structure of solder joints greatly affects the reliability of electronic packages. The impact of those various surface finishes on the micro-structure of SAC305 lead-free LGAs, BGAs and CSPs, were investigated. A clear correlation between PCB surface finish, micro-structure and reliability behavior was observed. The results assist in optimizing the design of packages and selection of materials that can lead to higher reliability performance of products.   While component footprint size continues to decrease year after year, power dissipation continues to increase.

Thermal interface materials (TIMs) are frequently used to increase the efficiency of heat transfer from the die to the thermal solution. In an effort to provide more realistic thermal resistance measurements, a variable load component level test fixture was developed for measuring the thermal resistance of TIMs. The micro-structure of each gap pad was also studied in conjunction with thermal resistance measurements to help explain TIM performance.

Another aspect for the advancement of packaging technology is the ever growing defect know as component warpage. This is the root cause for many manufacturing defects encountered by CMs who develop processes for the assembly of advanced products. While standards exist to address tolerable warpage, there are many devices that easily comply with the standards, as characterized utilizing the prescribed techniques, yet still produce HiP failures.

This talk looks to answer the questions: Can we assemble tomorrow’s technology with current tools?  Are we at a crossroad of accuracy for given material manufacturing techniques and assembly tools?  What novel materials are required?  Is there a convergence of semiconductor design and assembly with board assembly? Can we design quality into our device by optimizing materials and processes?

We answer these questions by looking at various case studies and the root cause of specific failures.


You may contact the author, Denis Barbini by barbini@uic.com or call +1 603-828-2289 . For more information on Advanced Process Lab, visit https://www.uic.com/solutions/apl/ or contact David Vicari (+1 607-761-4092/ vicari@uic.com).

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