2006 Reports

Downloads & Resources

Pb-Free Assembly with Loctite 3509 Corner/Edge Bond Adhesive
Author: Daniel Blass
Abstract: Loctite 3509 adhesive was used to bond the edges and corners of Pb-free BGA components to the PCB by dispensing prior to component placement and curing in the Pb-free reflow. This is the first pre-applied corner/edge bonding adhesive we have investigated that can be used in the hotter Pb-free reflow. Dots could not be dispensed because the adhesive was stringy and formed long tails as the needle moved to the next location. A short line dispense could be substituted to make corner bonds. These corner bonds were fragile and easily fractured. A full edge fillet around the component would be more robust but the fillets held the component up during reflow enough that assembly yields could be affected.

Effect of Annealing on Voiding in Cu3Sn
Authors: Liang Yin, Joseph Therriault and Ju Wang
Abstract: Pre-annealing of electroplated foils at 650°C has been shown to be effective to eliminate the voiding in Cu3Sn in subsequent high temperature storage. In this report, annealing temperature dependency of voiding level was investigated for two Cu foils having high propensity for voiding, in the temperature region of 250-550°C. Annealing time dependence was also evaluated for the two foils at 350 °C and 450°C, up to 20 hours. Void density of Foil 1 showed gradual decreasing trends with both annealing temperature and time, while Foil 44 exhibited a rather sudden decrease in the temperature region of 350-450°C. In both foils, the reduction of voiding level correlated well with grain growth during annealing. Discussions of grain growth and impurity distribution are also presented.

Pull Test Evaluation of Intermetallic Strength for SnAgxCuy Solder Balls on Ni and Electrolytic Ni/Au Pads
Author: Tia Korhonen
Abstract: Solder ball pull testing was done to evaluate the intermetallic strength between SAC solder bumps and electrolytic NiAu or bare Ni pads. The amount of copper and silver in the solder was varied in several ways to control which intermetallics formed and the final ball composition. Reflow time, peak temperature, and cooling rate were studied. Solid state aging to grow the intermetallic layers was also performed.

Cooling rate did not affect ball pull strength. Peak temperature did not have a consistent effect on pull strength. There were wide variations in pull strength and concerns about the quality of the soldering to the bare Ni for those samples. Changing the Cu composition had modest effects on pull strength. The highest Cu concentration, SAC309, was the only one that gave only IMC failures and no failures in the bulk solder. Reflowing for long times, 100 seconds over 217°C, gave the strongest intermetallics for the SAC305 and only solder failures were obtained at the standard pull rate. Intermetallic strength decreased with the thick intermetallics obtained by solid state aging for 4 weeks or more at 175°C.

Overview of Component Test Board 2006
Author: Michael Meilunas
Abstract: This report provides the basic design and construction details for Component Test Board 2006 (CTB2006). CTB2006 forms the interposing substrate used in the Unovis Solutions’ generic component construction process. Components created with CTB2006 have been and will continue to be assembled to Test Board 2006 for evaluating the thermal cycle and mechanical reliability of Pb-free solders.

Voids in Cu3Sn: Copper Screening Recommendations
Authors: Pericles A. Kondos, Liang Yin and Peter Borgesen
Abstract: Occasionally, solder joints on Cu pads may become seriously weakened by voiding within the intermetallic bonds. This depends somehow on the quality of the plated Cu, but nobody knows how to control that yet. A separate document outlines a series of conservative screening tests which allow the separation of “good” copper from “bad” or “questionable” copper. The times and efforts involved in these tests differ greatly, as do their effectiveness and accuracy. The present document makes recommendations as to an effective screening protocol.

Sporadic Degradation in Board Level Drop Reliability- Those Aren’t All Kirkendall Voids!
Authors: Peter Borgesen, Liang Yin, Pericles Kondos, Donald W. Henderson, Greg Servis, Joseph Therriault, Ju Wang and K. Srihari
Abstract: The sporadic occurrence and growth of voids within the Cu3Sn intermetallic layer formed when soldering to copper is the cause of growing concern for microelectronics manufacturers. Overlooked for decades, and commonly underestimated when observed, there are reasons why the phenomenon is becoming a threat to ever more products. In fact, while rarely severe the problem has been known to cost individual companies anywhere from tens to hundreds of millions of dollars.

The voiding has been shown to depend on some yet to be identified property of the plated Cu, rather than the solder, or materials, or the assembly process. Effective screening processes have been developed that would have prevented all the losses alluded to above, but there is clearly a long term need for us to learn how to control and preferably prevent the problem. We are busily researching potential remedies, but a safe resolution to this highly variable problem may well require a fundamental understanding of the underlying mechanisms.

The phenomenon is commonly referred to as Kirkendall voiding, albeit without any arguments or data to support this assumption. In the present work we argue, however, that there must be more to it than a simple ‘Kirkendall effect’. Along the way we present data showing Cu to be by far the dominant diffusing species in the Cu3Sn layer, a result which is important for the interpretation of experimental void observations. A review of the literature revealed only a single marker experiment contradicting this conclusion, and we argue that the ‘markers’ in that experiment could not have been at the Kirkendall plane.

High Speed Ball Shear Testing of SnAgxCuy Solder Balls Attached to Electrolytic Ni/Au Pads
Authors: Tia-Marje Korhonen, Pericles A. Kondos and Daniel Blass
Abstract: High speed ball shear testing was performed on lead-free solder balls attached to electrolytic NiAu gold pads. The primary interest was the study of intermetallic strength but the failure sometimes occurred in the solder instead of the intermetallic layer between the solder and the Ni pad. Most of the present work focused on varying the ball attach reflow conditions, such aspeak temperature, time above liquidus, and cooling rate, or varying the copper concentration in the solder sphere prior to ball attach. This initial survey employed only a limited number of samples for each parameter combination, so that statistical outliers could not be addressed.

For SAC305 solder, there was not a consistent trend among the various reflow conditions tested as far as the average intermetallic strengths were concerned. Failures generally occurred at the IMC layers but the location of the fracture within the IMC layer structure tended to vary across a pad. Some failures in the solder were also observed. Multiple reflows gave a slight drop in average shear strength but the difference was not statistically significant. Cooling rate did not affect shear strength.

Containing no Cu, SnAg balls only form a Ni3Sn4 IMC layer. SAC balls with 0.19% Cu and 0.34% Cu also had too little Cu to form any (Cu,Ni)6Sn5. Shear testing showed the (Ni,Cu)3Sn4 formed with 0.34% Cu to be slightly stronger than the (Cu,Ni)6Sn5/(Ni, Cu)3Sn4 structures formed with SAC305, but the difference was not always statistically significant. The SnAg and the SAC with 0.19% Cu both gave primarily solder failures, but at loads that showed the IMC to be stronger than the (Cu,Ni)6Sn5/(Ni,Cu)3Sn4 structures formed with SAC305.

The higher Cu content in SAC309 means that it should only form a (Cu,Ni6Sn5) IMC layer. These balls all failed at the IMC layer with a smooth fracture surface that appeared to contain two phases. The second phase may, however, be the underlying Ni. The IMC failed at a lower load than the (Cu,Ni)6Sn5/(Ni,Cu)3Sn4 structures formed with SAC305, but this difference may be associated with the greater leverage achieved in shear of the larger solder spheres.

The sequence in which the two layers in the (Cu,Ni)6Sn5/(Ni,Cu)3Sn4 structure are formed did not have a big effect on shear strength. This was verified by soldering first a SnAg ball to form a Ni3Sn4 layer, then removing the ball and soldering a SAC305 ball to the remaining IMC.

According to the literature incorporating some Au into the IMC structure may weaken it, but we found no significant effect on average shear strength. This was verified by etching off the Au from the Ni pad before attaching a SAC305 ball. The shear strength fracture surface was, however, much rougher than on a NiAu pad.

Reflowing for very long times led to spalling of the (Cu,Ni)6Sn5 layer from the (Ni,Cu)3Sn4 but did not produce very low average shear strengths. However, identical reflow conditions did lead to very large variations from sample to sample. The underlying IMC strength may in fact vary even more, the stronger joints leaving more solder on the pad after shear than the weaker ones.

Immersion Silver and Champagne Voids
Authors: Pericles A. Kondos and Joseph W. Therriault
Abstract: The reliability of joints formed on boards with Immersion Silver finish can be compromised by the occasional appearance of a large number of small voids between the pad intermetallic and the solder. Several samples from various sources and with different silver plating chemistries were studied in the Advanced Process Lab (APL) and the appearance of voids was correlated with features in the silver layer and the copper underneath. Our results were generally in agreement with literature reports. Although the reason for the formation of these voids is still unknown, empirical observations led to changes in the recommended plating conditions by chemistry suppliers in order to minimize this type of voiding. Although the problem might have been solved, a quick test can be used to verify that a particular batch of boards will not suffer from such voids after reflow.

Compatiblity Testing of BGA/CSP Underfills with Pb-Free Solder Pastes
Author: Daniel Blass
Abstract: CSP components were built with four Pb-free SAC305 solder pastes and underfilled with four underfills. The underfill layer was examined for defects, such as voiding or cracking. Flat-sections were made that removed either the component or the PCB. Low CTE rigid underfills tended to have fewer defects in the underfill layer. The higher CTE CSP underfills shrink enough after cure that voids form between the underfill and the solder mask of the PCB or component and cracks form within the underfill layer. A soft, low Tg underfill had the most shrinkage voids and cracks. The effect of the shrinkage voids and cracks will depend on the service requirements and the mechanical properties of the underfill.

Compatibility of the solder paste flux residues and the underfill is important. Flux residues were generally not observed in the flatsections but were found around the joints for some underfill-solder paste combinations. One underfill had small irregular shaped voids around the solder joints that might be caused by the flux residues. These voids occurred with all four solder pastes. Shrinkage voiding and cracking varied with underfill and solder paste selection. The solder paste that gave the most shrinkage voiding with one underfill gave the least underfill cracking with a different underfill.

Selection of Preferred Lead Free Alloy in Drop Test
Author: Brian Roggeman
Abstract: The transition to lead-free soldering brings about many complications. One in particular is the selection of the preferred lead-free alloy. Several different alloy compositions are available, with the Tin-Silver-Copper (SAC) alloy being the predominant choice. Variations in the amount of each constituent within a SAC alloy can have large impact on the mechanical behavior of the joint. Further, some doping agents have been proposed to enhance mechanical robustness or prevent sporadic degradation mechanisms.

Area array packages were tested under mechanical shock, or drop, to assess the mechanical reliability of various lead-free alloys. The effect of silver content in the joint was studied, as well as alloys containing doping elements. The drop test used was adapted from the JEDEC JESD220-B111 Board Level Drop Test Method. Detailed failure analysis was performed to gain a better mechanistic understanding to help with making more accurate generalizations.

Development of a Low-Temperature Drop Testing Technique
Author: Brian Roggeman
Abstract: Testing for mechanical reliability of electronics can be complex. Different loading conditions will invariably produce different results. One such variation is changing the test temperature to realistically duplicate service conditions. Lowering the temperature will generally increase solder strength but reduce ductility. The opposite is true for elevated temperatures. The changing of material properties may easily lead to changes in failure modes. Therefore, characterizing the reliability at a range of temperatures is preferred, especially if the product will be exposed to more than just room temperature.

An apparatus was built for testing the drop reliability of BGA components at lower than room temperatures. Results are presented, and new test protocols are suggested.

Mechanical Testing Overview
Author: Brian Roggeman
Abstract: Traditional reliability engineering has tended to focus on thermal cycling (and power cycling) performance, but today by far the most products tend to fail under loads not specifically associated with thermal expansion mismatches. Accordingly, there is an obvious need to establish a comprehensive understanding of mechanical robustness and reliability issues. Due to various damage mechanisms and loading conditions, a general solution may not be achieved.

The “Missing Ball” Phenomenon on Ni/Au Metallizations: A Review
Author: Pericles A. Kondos
Abstract: Occasionally, very early brittle failures are observed in bumps or joints on electrolytic Ni/Au pads, resulting in “missing balls” on unassembled components or in failed assemblies. The phenomenon was first described by Qualcomm, but has since been reported by other companies as well. The various publications and presentations dealing with this issue are reviewed, together with observations on problematic samples sent to the Advanced Process Lab by Consortium members. In order to discover the reasons behind the problem, working hypotheses are formulated based on common threads and trends. These trends include the appearance of bright “haloes” on the exposed pads and a darker phase, which is usually identified with the (Ni,Cu)3Sn4 intermetallic. It is the author’s opinion that the crack is inside this intermetallic very near its interface with the nickel, occasionally even exposing the metal underneath.

Reliability of Backward Compatible Solder Joints in Accelerated Thermal Cycles
Author: Michael Meilunas
Abstract: Backward compatible soldering is a process in which Pb-free devices are assembled to PCBs using Sn/Pb paste resulting in “mixed” alloy solder joints. This report discusses the reliability of three backward compatible assemblies evaluated in 0/100oC thermal cycles with 10, 30 and 60 minute dwells and -40/125oC thermal cycles with 10 minute dwells.

Mixed Alloy Process Manual 2006
Author: Michael Meilunas
Abstract: The following document provides material requirements, inspection guidelines and our current best process recommendations for the successful assembly of mixed solder systems with a focus on the parameters necessary to create reasonably reliable products.

There is often an interest in assembling with the lowest possible peak reflow temperature, while the peak temperature offering the best reliability seems to depend on the type of loading (mechanical or thermal) of primary concern. A reasonable compromise mayoften be a peak temperature of 220-230oC, at least for backward compatible systems, if the reflow profile is appropriately extended. Preferred methods for assembling forward and backward compatible systems are discussed with the understanding that a recommended No-Pb reflow temperature of ~245oC may not be an option due to temperature limitations of the printed circuit board and/or Sn/Pb bearing devices.

Effect of Oxygen Contentration in an Inert Reflow Environment
Authors: Ursula Marquez de Tino and Michael Meilunas
Abstract: The objective of this project is to evaluate new methods of nitrogen delivery during the reflow process in an overall attempt to reduce total nitrogen consumption without affecting assembly yield and product reliability. Two nitrogen supply techniques were evaluated with various degrees of oxygen contamination and compared to air only reflow. The results suggest that nitrogen gas need only be applied to the oven zones where solder is in its liquid state. The current experiment is an introductory project and considerably more work is planned on this topic.

Pad Cratering Overview
Author: Brian Roggeman
Abstract: Cracking of the laminate under the PCB pad is a reliability issue, related to mechanical stresses generated from either mechanical or thermal loading. The transition to RoHS compatible materials and processes compounds the problem as the materials are stiffer and more brittle. Resistance to cratering is affected by various degradation mechanisms, including multiple reflow and moisture exposure. The loading condition also plays an important role, as single overstressing is a different mechanism than cyclic loading. The relationship between pad size and strength is not trivial, so we cannot develop simple scaling factors. Clearly, the proper selection of laminate material can be critical in overall PCB reliability.

Pb-Free Process Guide 2006
Author: Michael Meilunas
Abstract: This document provides material requirements, inspection guidelines and process recommendations for Pb-free area array assembly based upon our consortium sponsored research which covered a range of laminate and flex based BGAs and CSPs with pitches down to 0.5mm including Wafer Level CSPs (WL-CSPs). Much of the following is also relevant to other components such as ceramic BGAs and 0.4mm pitch WL-CSPs, except that the latter may be assembled without the use of solder paste. Very different considerations apply to flip chip and MLF/QFN/LGA assembly for which separate process guides are provided.

Assembly cannot be viewed independently of quality and reliability requirements and this document offers critical comments and recommendations pertaining to thermal cycle testing.

This paper is a “living document” and is subject to change as new material sets become available during the transition to Pb-free assembly. Our current recommendations are to use the SAC305 alloy when possible, and the present guidelines are focused on convection oven assembly of components with common Sn/Ag/Cu alloys such as SAC405, SAC305, and SAC205 onto FR4 type printed circuit boards.

Effect of Assembly Parameters on Pb-Free Reliability
Author: Michael Meilunas
Abstract: Virtually all aspects of a BGA assembly process affect the long term reliability of the component. The effects of many factors are not readily apparent and are often overlooked. This report documents an experiment whose goal was to evaluate subtle differences in the assembly of BGA devices which may or may not impact the long term reliability of the solder joints. Specifically, three solder fluxes, two solder pastes and two reflow cooling rates were independently compared in an effort to determine if these factors significantly affected the reliability of Pb-free BGA devices.

2006 Pb-Free Update: Evaluating Accelerated Thermal Test Paramaters for Select Solder Alloys
Author: Michael Meilunas
Abstract: The following report describes an experiment performed on four Pb-free solder alloys with the intent of increasing our understanding of accelerated thermal cycle test conditions based upon package configuration.

Specifically, the current research investigates the effects of cyclic temperature extremes and dwell time by comparing -40/125oC and 0/100oC thermal cycles with 10, 30, 60, and/or 120 minute dwells on similar BGA-style packages. Three package configurations were evaluated: 1.0, 1.4, and 1.8mm pitch containing identical construction materials.

The simple package construction allowed for an introductory analysis of shear strain and shear strain rate as it pertains to the reliability of each solder alloy. This analysis was performed with the understanding that the three package sizes and two thermal cycles combined to produce six levels of shear strain in the outer most solder joints -where failure is most likely to occur.

Not surprisingly, the results indicate that the cyclic temperature extremes significantly affect the number of cycles to failure (CTF), but to what extent is due to cyclic strain or test temperature remains uncertain. As expected, the available thermal cycle failure data proves that increasing dwell time can significantly decrease mean CTF. However, the complete results of the extended dwell time tests (60 and 120 minutes) are not currently available and it is unknown if a further reduction in CTF will occur under all test conditions. The data also indicates that each solder alloy evaluated has a somewhat unique sensitivity to shear strain, i.e. some alloys perform comparatively better under ‘high’ strain than ‘low’ strain (and vice versa) in accelerated testing. Finally, a comparison of the strain rates encountered, coupled with previous research data indicates that strain rate was not the dominant factor affecting reliability in this experiment.

Lead Free Printed Circuit Board Process Manual
Authors: Wayne T. Jones and Peter Borgesen
Abstract: The transition to lead free soldering puts new demands on the laminate structures used, be they component substrates or printed circuit boards. In particular, there is great concern as to the potential for new or enhanced damage in assembly. Some of these concerns are obvious and testing or inspecting for them is straightforward, but others are much more subtle and/or may be very design, materials and component specific. Standard industry tests are found not to be very effective discriminators. Extensive research is ongoing to identify and characterize important damage mechanisms, and to define procedures to test for these, but meanwhile life must go on and practitioners continue to design and assemble new products.

The present document summarizes our current best recommendations for laminate materials selection and testing based on the results of our research results so far. This includes both our knowledge of specific materials and recommendations as to what else to test for, or have the supplier test for. Focus is on substrates and printed circuit boards constructed with multilayer lamination processes and common cost-effective material sets.

Using Warpage to Detect PCB Degradation
Author: Brian Roggeman
Abstract: Printed circuit board integrity is a critical concern during assembly. A live product may see several thermal excursions during its assembly cycle, and material degradation is likely to occur, especially at temperatures required for lead-free assembly. Visual surface inspection and cross-sectional techniques following mass reflow are the most common and straight forward methods for uncovering damage. However, these visual techniques give no indication of degradation if physical damage is not present. Previous attempts at correlating material properties (Tg, Tdeg, CTE, etc.) with laminate damage have thus far proven unsuccessful. Shadow-Moiré can be used to observe changes in warpage behavior with each successive reflow cycle, and that may uncover degradation not detectable by other means.

PCBs were subjected to multiple mass reflow with a ramp to spike (RTS) profile at 260 °C peak temperature. The warpage behavior of the PCB was measured after each reflow cycle over a temperature range of 25 °C to 150 °C. The purpose of this testing is to identify changes in the material behavior that may be an indication of degradation and/or damage not visible on the surface. It also serves as a potential qualification tool for realistic assembly conditions which see multiple thermal excursions. Changes in warpage behavior are correlated to damage assessment by cross-section and other optical methods.

Package on Package: An Introductory Evaluation of Stackable Package Technology
Authors: Michael Meilunas and Brian Roggeman
Abstract: The following report is intended to document recent investigations into Package on Package technology including component evaluation, board level assembly techniques and reliability testing.

Intermetallics and Cu3Sn Voids in Sb-Containing Solder
Authors: Pericles A. Kondos and Joseph W. Therriault
Abstract: Antimony was used as an additive to SAC solder in order to study its effect on the aging-induced Cu3Sn voiding. The initial tests were made with commercial CASTIN® solder spheres from two different sources and showed similar behavior, both reducing the voids seen in bumps on two void-prone substrates. On the other hand, use of SnSb solder paste with 5% Sb produced bumps with at least as many voids in the intermetallic as seen in SAC bumps but with different spatial distribution. Results with intermediate amounts of Sb indicated that there might be an optimum concentration of Sb around 1%. The intermetallic growth was also affected by the amount of Sb but in a complicated way which has not yet been fully explained. Based on the results of these experiments, Sb-containing solders do not appear to be a viable solution to the voiding problem.

Application of the Shadow-Moire Technique to Detect PCB Delamination and Blistering
Author: Brian Roggeman
Abstract: Printed Circuit Board (PCB) damage can form in a variety of ways. In areas of high copper density, such as vias or through-holes, the difference in CTE can cause delamination between layers. If the delamination does not also result in electrical failure, it may go undetected. Undetected delamination will reduce the overall integrity of the board, allow greater moisture uptake and may lead to other failure mechanisms such as corrosion and CAF growth. The Shadow-Moiré technique has been applied at elevated temperatures to monitor PCB surfaces for the onset of delamination. In some cases, the delamination recedes enough at room temperature that it cannot be resolved, or may be overlooked. The use of this technique as a screening test is proposed for panels that may be prone to this failure mode.

Tin Whiskering Overview
Author: Daniel Blass
Abstract: This document reviews tin whiskering and mitigation steps. There has been a large volume of whisker research over the past few years and several industry documents and standards have been developed. Despite this work, whiskering is not yet understood well enough to know how to properly test for whiskering, predict whether or not a tin finish will give whiskers, or the probability of a whisker failure.

Design Overview of Test Board 2006
Author: Michael Meilunas
Abstract: This report documents the basic design and purposes of Test Board 2006 (TB2006). TB2006 was developed by Unovis Solutions’ Advanced Process Laboratory in conjunction with Huawei Technologies.

Thermal Cycling Results for Underfilled and Edge-Bonded BGAs
Author: Daniel Blass
Abstract: A 30 mm FCBGA component with SAC305 solder balls was tested with underfills or corner/edge bonding reinforcements. Reworkable and non-reworkable underfills with a variety of mechanical properties were used. The thermal cycle was a one hour cycle between -40°C and 125°C. Some of the components were preconditioned by drop testing prior to the thermal cycling. Edge fillets at the corners or around the entire component were most robust, particularly with a rigid, low CTE adhesive. Even after 100 drops, the rigid fillet gave a 1.5X improvement in N63 compared to BGAs that were not reinforced or dropped. While underfilling improves drop resistance, thermal cycle reliability was reduced with all underfills. Rigid, non-reworkable underfills performed better than the soft reworkable underfills. One set of SAC305 BGAs assembled with a SnPb paste and underfilled with a soft reworkable underfill did much better than the same combination assembled with a SAC305 paste.

On the Cause of Voiding in Cu3Sn
Author: Liang Yin
Abstract: The occasional voiding in the Cu3Sn intermetallic compound during solid state reactive diffusion appears to be related to certain factors inherent to the Cu electro-deposition itself. The voiding level was reduced dramatically after pre-annealing of the unsoldered Cu at 650 °C for 2 hours. This led to the development of a significant number of large pores in any Cu with a high propensity for Cu3Sn voiding, and the final grain sizes were smaller in such Cu as well. Electro-deposited foils and electroplated foils showed the same trend. Annealing of a high purity wrought Cu foil showed grain growth that far exceeds any of the plated ones. Additional discussions on pore formation and grain growth are presented.

Voiding in Cu3Sn and Impurity Incorporation in Cu During Plating
Author: Liang Yin
Abstract: The Cu3Sn intermetallic compound layers formed on Cu-pads during soldering have occasionally been seen to develop voids during high temperature storage. Previous investigations have indicated that the root cause of the voiding is a yet to be identified factor inherent to the plated Cu pads. Pre-annealing experiments at 650 °C reported elsewhere suggested that the voiding is associated with the incorporation of some organic impurity during Cu plating. The present report offers a brief review of acid copper plating for PCB and IC metallization. A literature survey of impurity incorporation is then introduced, focusing on the effects of plating condition, additives interaction and geometry. Average impurity concentrations in Cu foils with known propensities for voiding were assessed by GDMS. In several Cu foils the voiding level was, however, seen to vary throughout the foil thickness. This might perhaps be attributed a non-uniform distribution of impurities. SIMS trace element analysis was performed on two electrodeposited foils and an electroplated foil. The voiding behavior of two high purity wrought Cu foils is also presented.

Voiding in Cu3Sn: Copper Screen Test
Authors: Liang Yin, Pericles A. Kondos and Peter Borgesen
Abstract: Occasionally, solder joints on Cu pads may become seriously weakened by voiding within the intermetallic bonds. This depends somehow on the quality of the plated Cu. In our assessment 5-15% of all plated Cu is in fact bad enough that it may be a problem for some applications. A series of conservative screening tests have been developed which allow the separation of “good” copper from “bad” or “questionable” copper. The times and efforts involved in the tests differ greatly, as do their effectiveness and accuracy. The individual tests are intended for use at various stages from supplier qualification to monitoring of batch to batch variations. The present document outlines and discusses the individual tests. A companion report offers recommendations as to actual test protocols. The reader is referred to other reports for supporting documentation and justifications.

Effect of Zn on Cu3Sn Voiding: An Update
Author: Pericles A. Kondos
Abstract: Last year we reported that the addition of a small percentage of Zn in SAC solder completely eliminated the formation of the voids often appearing in the Cu3Sn formed on copper pads after aging of Sn-containing joints. Several questions remained unanswered at that time, including the minimum percentage of Zn required, whether it would protect the PWB pads as well or it would all be consumed by the component pads, and whether its protective action was affected if the component-side pads were Nibased. The present report addresses these questions.

Area Array Rework Process Manual 2006
Author: Laurence A. Harvilchuck
Revisions from 2005 to 2006:

Comments regarding the next generation of reworkable underfills

Area Array Consortium 2006 Overview
Author: Peter Borgesen
Abstract: This report offers a brief summary of our 2006 efforts. References are made to the detailed reports issued on the various subjects, Gerber data for current test vehicles, and our codification software. All of this is included on the 2006 CD. References are also made to reports on previous years’ CDs, and to an on-line data base. The latter is continuously updated as test results on a range of laminate structures are generated.