Downloads & Resources
Component Underfilling Manual: 2005
Authors: Daniel Blass, Antonio Prats, Howard Chen and Peter Borgesen
Abstract: BGAs and CSPs have traditionally achieved good reliability simply through their design and assembly process and have not needed to use underfill. As reliability requirements have increased, more and more manufacturers have become interested in using underfill as a way to meet these new demands.
This manual borrows heavily from our flip chip-based Underfill Process Manual but there are important differences between underfill for flip chip applications and underfilling packages. The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and troubleshooting. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.
The Minimum Peak Reflow Temperature Required for Reliable Lead-Free Assembly
Authors: Laurence A. Harvilchuck, Michael Meilunas, Zulfikar Malik and K. Srihari
Abstract: The minimum peak joint temperature in mass reflow should exceed 235°C for reliable assemblies. Comparison of the 245oC and 235°C peak solder joint reflow temperatures resulted in an approximately 10% reduction in the characteristic assembly life. Reflow with a 240°C peak temperature was statistically equivalent to reflow with a 245°C peak temperature. Manufacturing tolerances will also need to be taken into account when developing a production profile to maintain this solder joint temperature. It must be noted that this study does not address mechanical robustness or lifetime under isothermal testing conditions.
Mixed Alloy Process Manual: First Edition – 2005
Author: Michael Meilunas
Abstract: The following document provides material requirements, inspection guidelines and our current best process recommendations for the successful assembly of mixed solder systems with a focus on the parameters necessary to create reasonably reliable products.
There is often an interest in assembling with the lowest possible peak reflow temperature, while the peak temperature offering the best reliability seems to depend on the type of loading of primary concern. A reasonable compromise may often be a peak temperature of 220-230oC, at least for backward compatible systems, if the profile is appropriately extended. Preferred methods for assembling forward and backward compatible systems are discussed with the understanding that a recommended No-Pb reflow temperature of ~245oC may often not be an option at all due to temperature limitations of the printed circuit board and/or Sn/Pb bearing devices.
QFN / MLF Process Guide 2005: A ‘Cookbook’ for Optimizing Assembly Yield and Reliability
Authors: Michael Meilunas and & Ashok Thiyagarajan
Abstract: The following paper provides detailed design and process guidelines for Quad-flat No-Lead (QFN) packaging based on a substantial body of work performed by the Area Array Consortium. The information presented is designed to supplement and/or supercede the generic guidelines often offered by the device manufacturers. This is especially true for fine pitch (0.4mm) assembly. The goal of this process guide is to improve first pass assembly yields while maintaining or improving the long-term reliability of the QFN devices. Recommendations concerning printed circuit board design, stencil design, and pick and place operations are discussed. The information presented is based on actual experimentation, but due to the many QFN design variations available, it is up to the end user to verify that a good, reliable assembly is achieved before incorporating the recommendations into a final product.
Pb-Free Process Guide: Second Edition – 2005
Authors: Michael Meilunas and Peter Borgesen
Abstract: The present document provides material requirements, inspection guidelines and process recommendations for Pb-free area array assembly based upon understanding and knowledge acquired through our consortium sponsored research. Components covered a range from laminate based BGAs to CSPs with pitches down to 0.5mm, including Wafer Level CSPs (WL-CSPs). Much of the following is also relevant to other components such as ceramic BGAs and 0.4mm pitch WL-CSPs, except that the latter would normally be assembled without the use of solder paste. Very different considerations apply to flip chip and MLF /QFN/LGA assembly for which separate process guides are provided.
Assembly cannot be viewed independently of quality and reliability requirements, and the document also offers critical comments and recommendations as to thermal cycle testing.
This paper is a “living document” and is subject to change as new material sets become available during the transition to Pb-free assembly. Our current recommendations are to use the SAC305 alloy when possible, and the present guidelines are focused on convection oven assembly of components with common Sn/Ag/Cu alloys such as SAC405 and SAC305 onto FR4 type printed circuit boards.
Design Overview of the Component Test Board (CTB-2005)
Authors: Wayne T. Jones and Michael Meilunas
Abstract: This report details and documents the CTB-2005 Component Test Board. The CTB-2005 is a two (2) layer, 0.018” thick, FR-4 (175o C Tg), base substrate designed specifically for use in evaluating component construction variability and assembly robustness in lead free applications. The board is a simple “print and etch” design utilizing a single core laminate, thus eliminating many outerlayer chemical processes including electroless copper and electrolytic copper build-up plating. The board is OSP finished with Entek Cu-106A and encapsulated in Taiyo PSR-4000 BN Solder Mask.
The PCB design primarily contains features for in-house production of “Dummy” Pb-free BGA and CSP test components. The component foot-prints are daisy chained to provide electrical continuity when assembled on the Mechanical Test Board (MTB-2005). The board also contains several quality control evaluation features to provide a baseline of fabrication quality. Sanmina-SCI, Owego, NY, was selected to build this board in early 2005.
The functional design of this board was developed by Universal Instruments Advanced Process SMT Laboratory as a collaborative of project qualification issues and requests submitted by 2005 Area Array Consortium.
Lead Free Printed Circuit Board Process Manual: Version 2005
Authors: Wayne T. Jones and Peter Borgesen
Abstract: The transition to lead free soldering puts new demands on the laminate structures used, be they component substrates or printed circuit boards. In particular, there is great concern as to the potential for new or enhanced damage in assembly. Some of these concerns are obvious and testing or inspecting for them is straightforward, but others are much more subtle and/or may be very design, materials and component specific. Standard industry tests are found not to be very effective discriminators. Extensive research is ongoing to identify and characterize important damage mechanisms, and to define procedures to test for these, but meanwhile life must go on and practitioners continue to design and assemble new products.
The present document summarizes our current best recommendations for laminate materials selection and testing based on the results of our research results so far. This includes both our knowledge of specific materials and recommendations as to what else to test for, or have the supplier test for. Focus is on substrates and printed circuit boards constructed with multilayer lamination processes and common cost-effective material sets.
Assessing PCB Robustness and Damage After Lead-Free Reflows by Peel and Pad Pull Testing
Authors: Wayne T. Jones and Brian Roggeman
Abstract: Lead-free assembly and rework processes often cause significant quality and reliability concerns when using existing PCB laminate systems. So far it appears that the multiple mass reflows often involved in lead free assembly tend to be the most damaging of these processes. Among the many types of damage encountered weakening of the solder pads and delamination at both surface and innerlayers have been some of the most common and critical. The latter is a commonly recognized failure mode, although detecting it does require cross sectioning. Degradation in solder pad robustness, on the other hand, is usually not intentionally tested for.
Pad pull and peel testing were studied with two potential applications in mind. One would be to detect delamination at an earlier stage, or perhaps even before it really starts, and with better statistics because it doesn’t involve cross sectioning. The other would be to detect any degradation mechanism affecting the integrity or robustness of assemblies to survive mechanical shock, drop, bending, and thermal mismatch induced loading. A range of laminate structures were tested and some polyimide structures were included for comparison.
We concluded that peel testing and, in particular, simple pad pull offer considerable valuable information but not a direct simulation of most of the damage mechanisms of concern. We do expect pad pull to simulate damage in bending quite well, and we show how damage in drop testing can be reproduced by fatigue testing at an angle.
Lead Free Mass Reflow and Printed Circuit Board Damage
Author: Wayne T. Jones
Abstract: With each successive thermal excursion in assembly, specifically high temperature reflow, laminate and dielectric materials give up some level of overall integrity, imparting cumulative damage to product. Multiple mass reflow of the bare PCB is widely accepted as the most representative and analogous assembly simulation method. Thermal ramping and peak temperature are fully controllable and generally understood to be the most influential parameters associated with PCB destruction in standard assembly processes. Switching to lead free assembly peak reflow temperatures pose an increasing concern, especially for large integrated assemblies where temperatures may approach 260°C somewhere on the board. We have chosen a profile with a gradual, linear ramp into a spike (RTS) to represent typical Pb-free solder assembly. Such profiles often yield better wetting with less thermal shock than conventional ramp-soak-spike profiles. However, the 260°C peak is quite aggressive and in many cases detrimental and destructive, to base PCB substrates (as well as componentry).
Undercooling of SAC Solder Joints and Possible Effects on Mechanical Behavior
Authors: Liang Yin and Tia-Marje Korhonen
Abstract: Mechanical properties of no-Pb solder joints are expected to vary, among other, with the degree of undercooling during cool-down from reflow. A brief study was therefore conducted of factors affecting the undercooling behavior of Sn-4.0Ag-0.5Cu (SAC405). Measurements showed the degree of undercooling to vary between 19 °C and 68 °C across a limited set of samples. Important factors were found to include solder volume, pad size and finish. Preliminary tests found at most a weak correlation between undercooling and solder ball pull strength, but potential effects on fatigue resistance have yet to be investigated.
Systematics of SnAgCu Based Assembly & Reliability
Author: Peter Borgesen
Abstract: Lead free solders are not simply variants of the solder we are used to, and using them is not simply a question of changing the reflow profiles. If we keep relying on the standards and ways of thinking developed for SnPb, serious misunderstandings and misjudgments will be made, and surprises will abound. We have, however, reached a level of understanding of the nature of SnAgCu solder joints that should help us do better than that.
The present report offers a brief outline of our current understanding of SAC solder and draws some important conclusions about practical consequences for both assembly and reliability assessment. The same understanding is also considered vital for the proper interpretation of many results of failure analysis.
Variability in SAC Mechanical Properties: Effect of Crystal Orientation
Author: Tia-Marje Korhonen
Abstract: One hundred pull tests were performed to 30 mil SAC 405 solder bumps on 25 mil ENIG pads. The pulled off bumps were saved, keeping track of the load to failure of each bump. The bumps that failed at very high or very low loads were cross sectioned and analyzed with Orientation Imaging Microscopy (OIM). There seemed to be correlation between the pull strength and the crystal orientation. Many of the “weak” bumps shared a common orientation. The “strong” bumps had several different orientations, which were all different from the “weak” orientation.
Accelerated Thermal Test Parameters II: Effects of Ramp Rate and Dwell Time on Pb-free Solder Alloys – Update 2005
Author: Michael Meilunas
Abstract: The following paper describes an experimental procedure used to evaluate the effects of thermal cycling test parameters on the reliability of Pb-free wafer level chip scale packages assembled to multilayered FR4 printed circuit boards. This report is a follow-up to “Accelerated Thermal Test Parameters I: Effects of Dwell Time on Pb-Free Solder Alloys” from the 2004 Area Array Consortium.
The results of “Accelerated Thermal Test Parameters I: Effects of Dwell Time on Pb-Free Solder Alloys” from the 2004 Area Array Consortium indicated that, for the assembly evaluated, the thermal cycle dwell time was inversely related to the cumulative cycle to failure (CTF). This relationship was established by comparing the CTF data acquired for 0-100oC cycling with dwell times of 15, 30, 120, 280, and 900 seconds . An equation was developed to predict the reliability (in N63.2) of the device as a function of dwell. Liquid-to-liquid thermal shock testing was used to minimize the effects of aging during the heating and cooling ramps. The results of the experiment produced good correlation with air to air thermal cycling, suggesting that the effect of temperature ramp rate on the Pb-free system was negligible, but insufficient data was available to fully support this claim at the time.
The current research further investigates the effects of temperature ramp rate and temperature dwell time by utilizing the same chip scale package and four 0/100oC air to air thermal cycling (AATC) tests. A similar methodology to that of “Accelerated Thermal Test Parameters I: Effects of Dwell Time on Pb-Free Solder Alloys” was employed to analyze and compare the data. The ramp rates evaluated included 10 and 20oC/min and the dwell times investigated were 5, 10, and/or 15 minutes at each temperature extreme.
As expected, the AATC failure data shows that increasing the dwell time decreases the mean CTF of the Pb-free wafer level CSP. This suggests that increasing the dwell time allowed more damage, in the form of crack growth, to accumulate per cycle in the solder joints -resulting in lower lifetime measurements. The data also indicates that the ramp rates evaluated, including the extreme rate achieved in liquid shock discussed in “Accelerated Thermal Test Parameters I: Effects of Dwell Time on Pb-Free Solder Alloys” , had a negligible effect on the reliability of the wafer level assemblies.
Thermal Cycle Results for Underfilled or Edge Bonded CSPs
Author: Daniel Blass
Abstract: Applications of fine pitch Wafer-Level-CSPs (WL-CSPs) may be limited by their low thermal cycling resistance. In this experiment, three approaches were used to try to improve the reliability of a fine pitch CSP component. Two approaches applied a flexible damming adhesive along the edges of the component, either at the corners or a fillet around all edges. A few components were capillary underfilled with a low Tg reworkable encapsulant. While these approaches have improved drop test reliability, each gave lower thermal cycle reliability than the non-reinforced CSPs.
Drop Test Results for Underfilled or Corner/Edge Bonded BGA Components
Authors: Daniel Blass and Brian Roggeman
Abstract: A 256 I/O, 30mm model flip chip BGA was tested on the consortium Mechanical Test Board. The model BGAs were balled with SAC 305 solder and attached to the test board with SAC 305 or eutectic SnPb solder. Drop testing was performed with a 500-G acceleration pulse (JEDEC JESD22-B111 Condition A). BGAs attached to non-solder mask defined (NSMD) pads would often fail in less than 10 drops while BGAs attached to solder mask defined (SMD) pads would often survive 50 drops. As would expected from these different drop results, the failure mode for NSMD pads was failure of the dielectric under the pad and cracking of the copper trace or pad. For the SMD pads, the solder mask holds the copper pad onto the board better and solder cracking is more likely.
To improve reliability with the NSMD pads, a number of underfill and edge bonding approaches were tried with encapsulants and underfills with various mechanical properties. To bond the edges and corners of the BGA to the PCB, a low modulus/high CTE encapsulant and a high modulus/low CTE encapsulant were used. Capillary underfills included both reworkable low modulus underfills and high modulus non-reworkable underfills.
Bonding only the BGA corners to the PCB did not improve drop test results. Full edge fillets or L-shaped fillets that extended 2.5mm to 5mm from the BGA corners did improve drop results. Fillets of Loctite FP6401, a low modulus encapsulant, helped 7 of 8 BGAs survive 70 drops. With a high modulus fillet of Loctite FP4451TD, 13 of 14 BGAs survived 100 drops. A visual examination after the drop test showed no damage to the fillets. Precise positioning is required when dispensing edge or corner bonds to ensure the deposit adheres to both the BGA and the PCB. This includes the impact of dispenser accuracy, fiducial selection, and tolerances on the component outline and position.
No BGAs underfilled with a reworkable underfill, Emerson & Cuming XE1218, failed after 100 drops. Two BGAs that were underfilled with Emerson & Cuming E1216 were drop tested. One failed after 66 drops and the other survived 100 drops. Both showed fillet cracking and likely delamination from the PCB solder mask. On several BGAs that were not tested, the E1216 fillet lifted off the solder mask during cure. This underfill may not adhere well to this particular solder mask or the adhesion may be compromised by the soldering flux residues. Other underfills have been used as well but the drop testing has not been completed yet.
Chip Capacitor Cracking in Lead-Free Assemblies
Authors: Laurence A. Harvilchuck, Santosh Anil Kudtarkar and K. Srihari
Abstract: Multilayer ceramic chip capacitor assemblies are bend tested to determine whether the stiffer SAC305 solder joints promote flex cracking of the capacitors over eutectic SnPb-soldered assemblies. Results indicate greater resistance to flex cracking for capacitors assembled with the SAC305 alloy than those assembled with the eutectic SnPb alloy, leading to the hypothesis that the SAC305 joints may be under compressive, rather than tensile, forces after assembly.
Correlating Cu and Cu3Sn Properties with Voiding
Author: Eric J. Cotts
Abstract: In order to correlate the voiding behavior with the properties of Cu substrate/foil and the Cu3Sn intermetallic compound formed during aging, X-ray diffraction analysis was utilized to characterize the stain state and the mean grain size of Cu. No relation could be found between Cu microstructure and the propensity for voiding. Microstructural analysis of Cu3Sn and voiding behavior were studied by optical and scanning electron microscopy. Submicron columnar Cu3Sn grains were identified in some samples using cross-polarized imaging technique.
“Effect of Solder “”Dopants””, Including Zn, on the Voiding in Cu3Sn”
Authors: Pericles A. Kondos and Tia-Marje Korhonen
Abstract: Several different solder compositions made from the same basic SAC alloy with minor additions of other elements were tested as a method to eliminate the voiding in the Cu3Sn. None of them seemed to work, except the zinc-containing alloy. Before this alloy can be proposed as a solution, its behavior regarding solderability, long-term effectiveness and reliability must be investigated. Some tests have been concluded and more are in progress to investigate the performance of Zn-containing SAC. It seemed that indeed the addition of Zn completely suppressed voiding even in the most void-prone types of Cu and after prolonged aging. Reliability tests are ongoing.
Effect of Warpage on Pb-Free AATC Reliability
Author: Michael Meilunas
Abstract: Most lifetime analyses analyzing CSP reliability fail to recognize the significance of out-of-plane displacement, or warpage as it pertains to thermal cycle performance. Instead, the focus has been on in-plane displacements due to coefficient of thermal expansion mismatches between the package body and printed circuit board.
The following document describes an experiment utilizing three CSPs which produced similar in-plane strain in thermal cycling. It was assumed that the crack growth rate within the solder joints would be similar, thus the larger packages with larger attachment pads were expected to survive more thermal cycles than the smaller packages. Tests determined that all the devices performed poorly in thermal cycling, but unexpectedly the larger devices failed much sooner than the smaller devices.
Analysis indicated that the devices warped significantly in thermal cycling. The devices were found to warp with similar radii of curvature which means that the solder joints in the larger packages were subjected to greater out-of-plane stress and strain. The estimated load created by the warpage was significant and explains the reduced reliability of the packages.
Additional work is ongoing. Similar devices that do not warp are being studied in order to quantify the reliability reduction due to warpage.
Drop Testing of Underfilled and Edge/Corner Bonded BGAs: Jabil Test Board
Authors: Daniel Blass, Brian Roggeman, Howard Chen and Antonio Prats
Abstract: A 225 I/O 27mm PBGA was attached off-center on a 102mm x 102mm board that was 1.5mm thick. Drop testing was performed with a 2900-G acceleration pulse (JEDEC JESD22-B111 Condition H). The board was fixed at two opposite corners in the test. As assembled, the eutectic SnPb BGAs failed in 8 to 31 drops with a variety of failure types, solder cracking, cracking along the pad intermetallics, fracture of the dielectric under the pads, or fracture of the copper pads or traces.
An experimental encapsulant from Emerson & Cuming was used to bond the corners or edges of the BGA. It is a viscous encapsulant that will not underfill by capillary action. The stated mechanical properties include a low Tg of 25°C and a modulus of 0.6GPa. The CTE below Tg is 90ppm/°C and CTE above Tg is 210ppm/°C. This encapsulant can be dispensed onto the motherboard before BGA placement and cured in a SnPb reflow. While more simple than underfilling, this may affect assembly yields since the adhesive holds up the part during reflow and the solder joints were several mils taller with this process. Drop resistance increased and BGA failure was delayed until after the edge fillets or corner dots had cracked. The time to failure increased with increased bonding area between the BGA and motherboard. In general, a corner dot is less efficient than adding a fillet that extends several mm from the corners of the BGA. Corner dots applied after BGA attach improved drops to failure to 23 to 64 drops. Corner dots applied before BGA placement improved drops to failure to 33 to 85 drops. A full edge fillet applied after BGA attach improved drops to failure to 58 to 164 drops. A full edge fillet applied before BGA placement improved drops to failure to 132 to 206 drops.
Some BGAs were underfilled with a capillary underfill, Ablefill 8807. This is a high modulus, low CTE underfill that is not reworkable. Two underfilled BGAs were dropped 150 times with no failure or observable damage. The motherboard had open plated through hole (PTH) vias under the BGA which lead to many voids in the underfill layer. This could be resolved by plugging and tenting the vias.
Improving CSP Mechanical Robustness by Various Underfill and Edge Bonding Techniques for a Medical Application
Authors: Daniel Blass and Wayne Jones
Abstract: This project investigated methods to improve mechanical robustness of CSPs. The test vehicle was a medical product with a high density 4 layer polyimide substrate. After component attachment, the populated circuit is mounted to a frame through the rest of the manufacturing process and eventually enclosed. The reinforcement should protect the CSP solder joints from damage by inadvertent deflection of the mounted flex circuit.
Four methods were used to reinforce the CSPs and a pull test was used for comparison. The four methods were capillary underfill, no-flow underfill, pre-applied corner dots, and post-applied edge fillets. The capillary underfill and edge fillets were low Tg, low modulus adhesives while the no-flow and corner dots both had higher moduli. With both the no-flow and corner dots, the solder mask delaminated and tore from the polyimide circuit. The low Tg capillary underfill cracked through its fillet and then along or near the bottom of the CSP before the solder joint would fail. The flexible edge fillets offered very little improvement since the fillet deformed enough to allow solder joint to fail before the fillet. A higher modulus material would be more successful and would have likely changed the failure location to the polyimide-solder mask interface.
Implementing one of these approaches depends on the details of the circuit board and component. Closely spaced components around the CSP will limit the ability to dispense fillets around the component. If there is room, dispensing an L-shaped fillet around the corners may give enough reinforcement. Pre-applied corner dots or lines will have space requirements around the CSP and/or between the edge of the CSP and the ball array. Additional pre-applied adhesive increases reinforcement but may affect assembly yields. Capillary underfill can be dispensed anywhere around a component where there is room and the underfill will flow under the CSP from that point. Whether capillary or no-flow, underfill volume control is needed on a high density board to avoid wetting to and underfilling nearby components.
Memory Effect in SAC Solder Joints
Author: Pericles A. Kondos
Abstract: Because of the fact that intermetallic particles in SAC balls can be very large, the possibility exists that some of them will survive reflow, giving the resulting joint a “memory” of the microstructure of the original ball and inconsistent or unpredictable properties. The present work looked for differences in the microstructure of joints in assemblies made with components that themselves differed in microstructure but were identical in other respects. Ag3Sn platelets were used as a marker of these differences; many combinations of solder alloys and pad metallizations were examined. Once it was established that there was, indeed, difference in the microstructure, reliability tests with the two types of assemblies were conducted. These tests looked both at failures and at the extent of cracking in joints that had not failed yet.
Mixed Alloy Reliability Update 2005: Feasibility of Low and Moderate Peak Reflow Temperatures & Sensitivity to AATC Temperature Extremes
Author: Michael Meilunas
Abstract: There continues to be a strong interest in minimizing peak reflow temperatures when soldering SAC area array bumps with a eutectic SnPb solder paste. Until now we and others have strongly advocated for peak temperatures near or above 240oC to ensure complete mixing and optimum thermal cycling performance, but we may have found an alternative.
Pb-free BGA, CSP and WLCSP devices were assembled to test boards using Sn/Pb paste volumes chosen to create Sn/Ag/Cu/Pb solder alloys with a nominal concentration of 2.7 – 3wt% Pb. Three reflow profiles were compared in terms of resulting thermal cycling performance: a “standard” Pb-free process and two “low temperature, long dwell” profiles developed specifically to better mix solder alloys at sub 245oC reflow temperatures.
As in previous work air-to-air thermal cycle testing showed the mixed solder alloys to be significantly less reliable than the “pure” Pb-free and Sn/Pb alloys. However, maintaining a peak reflow temperature of 221oC for 30 seconds was found to produce a mixed alloy that was just as reliable as one created using a 245oC peak temperature. A peak reflow temperature of 211oC, on the other hand, is still not recommended as even an extended profile led to low reliability.
A strain based approach to evaluating reliability was also undertaken with the mixed alloy data. This approach compared the results of a 0/100oC and a -40/125oC thermal cycle test by evaluating different assemblies that experienced a similar cyclic strain range. The results of this analysis indicate that the cyclic strain range is more important than the actual cyclic temperature swing in determining reliability. It also indicates that low strain ranges favor Pb-free systems and high strain ranges favor the Sn/Pb system in accelerated thermal cycle testing.
Solder Bump Pull Test and Shear Fatigue Evaluation of Mixed Solder Mechanical Properties
Author: Tia-Marje Korhonen
Abstract: Mechanical properties of mixed solder were studied by solder ball pull tests. SAC spheres were reflowed with eutectic PbSn solder paste on Cu pads, resulting in solder bumps with Pb contents ranging from 5% to 14%. All of the mixed solder bumps were stronger than comparable SAC solder joints. Two different pull rates were used, 0.5 mm/sec and 15 mm/sec. The slower pull rate typically resulted in failures through the solder. With the higher pull rate, fractures through the intermetallic compounds were also seen. Solder pastes from four different suppliers were used, and significant differences were seen in behavior of bumps reflowed with different solder pastes. Reflow peak temperature and ambient had a large effect in pull strength, and the effects were interdependent. Peak temperature of 220 oC resulted in higher pull strengths than 240 oC when the joints were reflowed in nitrogen. But for joints reflowed in air, the effects were reversed and the joints reflowed in 240 oC had higher pull strengths than joints reflowed in 220 oC.
Evaluation of Pb-Free Assemblies in Drop Test
Author: Brian Roggeman
Abstract: A brief study was conducted of some of the fundamentals of drop testing of area array assemblies. The dynamics of the assembly during drop was observed with the use of strain gages and accelerometers. The dynamics were found to vary with drop height. The resonant frequency increases with height as the assembly gets stiffer at higher strain rates or larger deformations. However, the input frequency increases faster and once it exceeds the resonance higher order modes become more prevalent, causing a superimposed vibration in the PCB.
First tests were conducted on area array assemblies with lead free solder joints (Sn/4%Ag/0.5%Cu and Sn/3.8%Ag/0.7%Cu) on Cu pads. The samples were subjected to JEDEC style shock conditions, and monitored for electrical failure. As is not uncommon, none of the joints failed within the solder. Rather failures occurred within the intermetallic layers on the contact pads, by fracture of the pads or connecting traces and/or by ‘pad lifting’ (failure of the PCB ‘buttercoat’ under the pads). As expected, the number of drops to failure decreased with increasing shock input. The data was well represented by an empirical power fit. Effects of varying component stiffness were quantified too.
Quantitative Analysis of Cu3Sn Voiding in Substrate 9
Authors: Pericles A. Kondos and Joseph W. Therriault
Abstract: Substrate 9, the substrate with the highest propensity for voiding, was used in a series of experiments involving placing SAC spheres of appropriate size on its pads, reflowing them, aging samples for various times at various temperatures, and analyzing images of cross-sections for voids in the Cu3Sn. The fraction of interface that was covered by voids was determined from these images and the time for it to reach a particular value was determined for each aging temperature. It was found that these times followed reasonably well an Arrhenius curve over the entire temperature range.
Voids in Cu3Sn: A Copper Screening Test
Author: Pericles A. Kondos
Abstract: A conservative screening methodology has been developed which allows separating “good” copper from “bad” or “questionable” copper. In the present context “good” copper is explicitly defined as material that can be soldered with SAC or eutectic SnPb without the Cu3Sn weakening too much afterwards due to void growth. Not addressed is an alternative degradation mechanism that does not involve measurable voids.
The proposed test is adaptable to user specific reliability requirements, but it is illustrated for a particular set of reasonable reliability requirements. A step-by-step description is given, together with the rationale behind each step and with other considerations regarding extrapolation to service conditions etc. At the end, the technique is summarized in a kind of recipe.
Voiding and Intermetallic Strength of SAC Solder on Cu Pads
Authors: Tia-Marje Korhonen and Peter Borgesen
Abstract: The present report addresses the use of ball pull testing to assess any abnormal weakening of the intermetallic structures bonding a SAC solder ball to a Cu pad. Such weakening may be caused by voiding within the Cu3Sn layer or it may be a result of another mechanism not associated with voiding.
12 mil and 30 mil SAC 405 solder spheres were reflowed on substrates with Cu pads in order to form solder bumps for pull testing. In a previous study, moderate to severe voiding in the Cu-Sn intermetallics had been observed for some of the substrates. The substrates were aged for up to 12 weeks at 70, 125, 150 and 175 degrees Celsius. The pull test results of the aged substrates were compared to un-aged substrates, to determine possible effects of voiding. In the cases where two failure modes were observed, statistical analysis was used to separate the measured pull strength distribution into separate distributions for the two failure modes. Fracture surfaces were studied with SEM and EDS to determine where the failure occurred. Metallographic cross-sections were utilized to determine amount of voiding at different aging conditions, in order to correlate that with pull test results.
Under conditions where the joints initially failed in the solder, a first indication of voiding would be a change in failure mode from solder failure to an interfacial failure. As the voiding progressed, the pull strength would also decrease. However, a moderate amount of voiding did not cause any significant change in the pull strength. Only after severe voiding was a large decrease in the pull strength observed. Furthermore, both solder and intermetallic strengths tended to decrease with aging, and an increased rate of intermetallic failure was not always an indication of voiding. For joints that exhibited interfacial failures even before voiding became apparent, the contribution of voids would be to change the specific location of the crack path. Initially the failure would occur within the Cu6Sn5 intermetallic, near the interface between the two intermetallics. After sufficient voiding a change in failure mode was observed, and the separation occurred within the Cu3Sn layer.
Voids in Cu3Sn: A Brief Overview
Authors: Pericles A. Kondos and Liang Yin
Abstract: The ongoing study of voiding in the Cu3Sn of solder joints on Cu pads has already generated an enormous amount of information, which is presented in several reports. A brief overview summarizing the results is given here. Topics studied included prevalence and seriousness of voiding, factors affecting it, variability and consistency, time evolution and temperature dependence, ways of eliminating voiding, and a test for screening copper for voids.
Voids in Cu3Sn: A General Overview
Authors: Pericles A. Kondos, Joseph W. Therriault and Santosh Anil Kudtarkar
Abstract: Recently, a new problem surfaced when soldering on Cu substrates, namely the appearance of voids in the Cu3Sn that forms on the pads during high-temperature storage. These voids occasionally can be so abundant that they have an adverse effect on the reliability of their joint. A comprehensive study was undertaken by the SMT Lab to determine the extent of the problem and understand the underlying mechanism, so that a solution can be found. Several reports in addition to this one present the results. In this first year of the project many different types of Cu were studied and the effects of assembly parameters on the voiding were investigated. It was found that voiding depended only on the properties of the copper. The voiding behavior of a limited number of substrates was studied quantitatively but semi-quantitative observations were made for many more, with special emphasis on the variability of the voids. An effort to correlate plating method/parameters with the corresponding voiding was also started.
“Voiding in Electrodeposited Copper Foils, Part I– General Survey”
Author: Liang Yin
Abstract: As a part of the effort to characterize the occasional voiding phenomenon in the Cu3Sn intermetallics formed between the Cu6Sn5 and the Cu in soldering and to understand theunderlying mechanisms, twenty six electrodeposited (ED) Cu foils and six laminates from various manufacturers were investigated. A significant fraction of the foils exhibited moderate to severe voiding, but some showed very little. The voiding behavior was not found to be dependent on foil manufacturer; different foils from one manufacturer made by nominally identical processes may behave differently. The degree of voiding was observed to increase with time and temperature.
“Voiding in Electrodeposited Copper Foils, Part II– Quantitative Analysis”
Authors: Liang Yin and Ju Wang
Abstract: In order to predict the degree of voiding in Cu3Sn at service temperatures, voiding behavior of four electro-deposited foils at high temperatures (>100 °C) were quantitatively analyzed. An Arrhenius model has been shown to agree with the data reasonably well in the temperature range of 125 – 205 °C for Foil 1, for both interfacial voiding and total voiding. The results of other foils indicates that the degree of voiding increases with temperature and time overall. In the mean time, the ratio of interfacial voiding to total voiding decreases with temperature and time.
Voiding in Electrodeposited Copper Foils Part III — Investigation of Underlying Mechanisms
Author: Liang Yin
Abstract: The occasional voiding in the Cu3Sn intermetallic compound formed during solid state reactive inter-diffusion is believed to be related to certain factors inherent to the Cu electro-deposition itself. In order to develop suggestions to eliminate or minimize the adverse effect of voiding on solder joint reliability, experiments were conducted on electro-deposited (ED) foils to investigate possible underlying physical mechanisms. High temperature pre-annealing of a foil at 650 °C was shown to reduce the degree of voiding dramatically.Surface contamination, impurities, fine grain structures and other defects associated with the surface region (< 8 mm) of ED foils were found not to be the primary cause of voiding. An external tensile stress during aging was shown to reduce the degree of voiding in a foil by 25-40 %. Cold rolling of ED foils appeared not to have significant effect on voiding.
Voiding in Multilayer Cu
Author: Pericles A. Kondos
Abstract: Substrate 1 was a group of boards with Cu/OSP-finished pads that consistently produced many voids in the Cu3Sn layer upon high-temperature aging of assemblies. It was used to study quantitatively this Cu3Sn voiding issue. Samples with either SAC or Sn/Pb spheres soldered on them were aged at various temperatures for various amounts of time, cross-sectioned, imaged in an SEM, and the voids were counted and measured. The thickness of the intermetallics formed on the pads was measured as well. It was discovered that the Cu pads consisted of three layers of Cu, and depending on the solder composition and aging conditions the Cu/Cu3Sn interface could be in any of these layers. The results of the measurements were used to investigate the temperature dependence of voiding. Differences between the two solder types and complications in the SAC group were attributed to the multi-layered structure of the pads. The distribution of voids across the Cu3Sn was used to draw conclusions about relative diffusion rates and about the mechanism of intermetallic formation.
Assembly and Reliability of Wafer Level CSP Bumped Using Kester 9690 No-Clean Polymer Flux
Authors: Laurence A. Harvilchuck, Santosh Anil Kudtarkar and K. Srihari
Abstract: Applications of fine pitch Wafer-Level-CSPs (WL-CSPs) may often be effectively limited by their low thermal cycling resistance. One way of improving on this may be to add a ‘polymer collar’ around the base of the solder balls, but that becomes increasingly challenging as the solder ball pitch is reduced. The applicability of an experimental polymer flux material originally developed for BGAs to a 0.5mm pitch WL-CSP was investigated. The achievable collar height was found to be extremely limited. The thermal cycling performance of wafer level packages bumped with polymer flux material as then compared to ones without polymer flux material.
Minimizing Reflow Temperature for Reliable Lead-Free Rework
Authors: Laurence A. Harvilchuck, Michael Meilunas, Zulfikar Malik and K. Srihari
Abstract: The minimum peak joint temperature in rework should exceed 235°C for reasons of lifetime under thermal excursions. Rework with a 235°C peak temperature led to a minimal, though still significant, reduction in the component life compared to that achieved in mass reflow or rework with a 245°C peak reflow temperature. Reflow at a peak solder joint temperature of 250°C yielded an additional increase in reliability, though concerns exist regarding assembly or substrate durability at these elevated lead-free reflow temperatures. When contrasted with mass reflow processes, no significant difference was noted between the lifetimes of the components reworked under nitrogen and those assembled by a flux-only mass reflow process in air.
Area Array Rework Process Manual
Author: Laurence A. Harvilchuck
- Details regarding rework of Quad Flat No-Lead (OFN) components:
- Thermometry and profile temperatures, including specific target temperatures for improved reliability of reworked assemblies
- Solder Replenishment for leadless packages on repopulation
- Enhanced section on component reballing in the course of rework:
- Thermal profiling issues in reballing
- Site redressing and solder scavenging concerns on substrates
- Alloy mixing when reballing components
- Reliability of reballed components
Author: Daniel Blass
Abstract: This report summarizes a research project on a process for soldering gold stud bumped flip chips. The process was attractive because it avoids the up-front expenses (UBM, masks, redistribution layers, etc.) for solder bumping a small number of wafers. Stud bumped flip chips were dip-fluxed and placed onto flip chip pads bumped with a Pb-free SnAgCu solder alloy. The joints are formed during mass reflow and the chip is subsequently underfilled.
This project focussed primarily on the assembly process. For successful assembly, a relatively large amount of solder must be applied to the substrate pad. As the solder volume is reduced, the Au-Sn joints tend to fracture between the end of reflow and underfill curing. This prohibits using this approach for fine bump pitches and limits the attractiveness of the approach. With sufficient solder, assembly yields were good but reliability results were not as robust as with solder bumped flip chips.
The microstructure of the solder joints are dominated by metallurgical reactions of gold from the stud bump, tin from the tin-rich solder, and the Cu or Ni from the substrate pad metallurgy. The microstructure also strongly depends on the reflow temperature profile, the volume of solder, and the size of the stud bump. Dominate phases in the joint after assembly may be Sn-rich solder or gold-tin intermetallics, AuSn4 or AuSn2. After assembly, thermal aging (including temperature cycling) will allow solid state transformation occur with gold diffusing into the solder joint and phases will be converted to more gold-rich intermetallic compounds (Sn-rich to AuSn4 to AuSn2 to AuSn). On nickel pads, the AuSn4 phase tends to form fine, sharp edged platelets while copper pads give smoother, thicker platelets and more favorable joint shapes.
Kirkendall voiding was commonly observed at the boundary between the gold stud-bump and the AuSn phase. These voids are a long-term reliability concern but were not studied in this project.
Soldering of fine pitch gold stud-bumped flip chips is possible by other processes. Shinko Electric offers contract assembly of multi-chip modules using a proprietary assembly process. This process, apparently using a die bonder, is slower than placement followed by mass reflow but it allows soldering of gold stud-bumped at very fine pitches. This project has not examined this assembly process or the reliability of the soldered stud-bump joint.
Cu-Sn Intermetallic Summary
Author: Peter Borgesen
Abstract: Soldering to Cu (say on a PCB pad) may lead to sporadic problems at an opposing Ni pad (on the component), but this is beyond the scope of the present text. Intermetallic problems associated with soldering to Cu alone are relatively rare. Still, a survey of over a hundred different Cu samples from a wide range of sources showed about 10% to develop sufficiently severe voids in the Cu3Sn intermetallic bond to be a concern for many applications. An apparently independent phenomenon will occasionally lead to a weak intermetallic right after reflow. These phenomena have been the focus of extensive research efforts, resulting in a series of detailed reports. The present document briefly summarizes these.
Flip Chip Assembly Manual
Authors: Daniel Blass, Antonio Prats, Peter Borgesen, and Pericles Kondos
Abstract: The following presents the framework for a comprehensive manual on the assembly of flip chips onto organic substrates. This manual is intended as a ‘living document’ which will continue to be updated as new knowledge is gained and should be viewed together with existing manuals focused on underfilling of flip chip assemblies and with so-called no-flow encapsulants. At the present stage emphasis is still on eutectic Sn/Pb based assembly, for which our data base and knowledge is by far the most complete, but smaller sections on no-Pb solder and Au stud bumped based assembly will grow considerably over the coming year. Considerable revisions are anticipated over the coming months, based among other on feedback from Consortium principals, and the final format will not be established until the contents are reasonably complete.
Evaluation of Loctite Hysol FF2300 No-Flow Underfill for Pb-Free Soldering
Author: Daniel Blass
Abstract: The Loctite FF2300 reflow encapsulant was evaluated for its Pb-free soldering performance and reliability. This encapsulant is capable of soldering Pb-free components but only in relatively cool or short reflow profiles. The process window is not wide enough for most applications. Flip chip assemblies built with this encapsulant failed very early in reliability testing.
Flip Chip Underfill Process Manual: 2005
Authors: Daniel Blass, Antonio Prats, Peter Borgesen, Sandeep Tonapi, Pericles Kondos and K. Srihari, Ph.D.
Abstract: The capillary flow-driven flip chip underfill process may be taken to include the selection of equipment (dispenser) and material. Creation of the process certainly involves specification of parameters such as bakeout requirements, substrate temperature, needle size, dispense paths (height above the substrate, distance to chip edge, length of pass), dispense rate, needle temperature, volume in each pass, timing of passes, cure parameters. Optimization of the process and specification of the process windows should minimize important variations and account for the inevitable variations (statistics and tolerances).
The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and troubleshooting. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.
The individual sections of this document are carefully organized to minimize the amount of experimental work actually required to reach your goals.
Moisture/Reflow Sensitivity Level Test Results
Author: Daniel Blass
Abstract: The ability to survive a standard moisture-reflow sensitivity test with a peak temperature of 260oC in a flip chip assembly with no-Pb joints is proving an effective discriminator between underfills. Of course, the performance depends on chip size, solder joint pitch and standoff. It also depends on flux selection, solder pad finish, and processing.
4 experimental underfills were evaluated for voiding and self-filleting, then tested first in a Level 3 MSL test with a 260oC peak and subsequently in Liquid-to-Liquid Thermal Shock: RP655-6 and RP655-7 from Ablestik, MTM 9086-66 and MTM 9086-71 from Lord. These materials were studied with different combinations of no-clean fluxes, solder alloy (SAC and SnPb), solder mask and two different chips: A 5mm perimeter array chip with 88 bumps, and a 12mm full area array chip with 1064 bumps.
Reflow Encapsulant/No-Flow Underfill Manual: 2005
Authors: Daniel Blass and Antonio Prats
Abstract: This is designed as a companion to the Underfill Process Codification. The aim is to present a guide to reflow encapsulant evaluation and process development. The focus here will be to highlight the differences, and to provide some simple and relatively quick characterizations that are necessary for reflow encapsulants. However, this should not be taken to mean that the establishment of a detailed and broad knowledge base is not important. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.
This document will also provide guidance for more detailed tests that will help with process development.
“Thermal Shock Testing of Flip Chip Assemblies with SNPB, SAC, and SNCU Solder”
Author: Daniel Blass
Abstract: Flip chip assemblies were built on thin substrates with eutectic SnPb, eutectic SnCu, and SAC 305 solder alloys. The 12mm chip had 1064 bumps an in area array pattern.
Soldering trials were performed with the SnCu solder on Cu-OSP and ENIG pad finishes with three no-clean tacky fluxes. The assembly process for the SnCu is similar to that used with SAC with peak temperatures of 242°C to 264°C and times over liquidus (227°C) from 44 to 71 seconds. The flip chips were soldered in a nitrogen ambient with less than 50 ppm O2. Joint height was comparable for all three solders but joint shape was more variable for the SnCu.
Flip chips assemblies for liquid shock testing were built on a 16 mil thick circuit board. The test board had Probimer 77 solder mask and ENIG NiAu pad finish. The flip chips were underfilled with 5 different underfills. With a high CTE underfill (45ppm/°C), all flip chips with SAC and SnCu solder failed by 500 cycles while chips with SnPb solder lasted more than 1500 cycles before a chip failed. With the remaining underfills, there were only slight differences in failure times between the three solder alloys. In acoustic microscope images, there were more “missing joints” with the SnCu and SAC after liquid shock testing than for the SnPb. This did not lead to more electrical failure in room temperature resistance testing but would likely have given earlier failure times if in-situ resistance monitoring were used.
In-Situ Thermal Characterization of Interfaces: An Update
Authors: Laurence A. Harvilchuck, Peter Borgesen, Santosh Anil Kudtarkar, K. Srihari and Eric Cotts
Abstract: In-situ thermal measurement offers the promise of direct measurement of the temperature drop across the thermal interface and a more precise assessment of the thermal conductivity at the interface. Resistance temperature devices can be patterned on the interface surfaces and the resulting assembly evaluated for thermal performance on both global and local levels. The ability to assess the impact of process induced defects on the local thermal performance will aid in the optimization of automated interface assembly processes. A test system consisting of test die and associated fixtures was designed and constructed in order to evaluate the local thermal conductivity of interfaces assembled on mass production equipment.
Process Induced Defects in Thermal Interface Assembly
Authors: Laurence A. Harvilchuck, Santosh Anil Kudtarkar and K. Srihari
Abstract: Thermal interface materials quite commonly do not perform as well in realistic applications as suggested by their data sheets. This is usually ascribed to defects such as voids and filler density variations. We are particularly concerned with determining to which extent and how the automated assembly process may affect the defect level. The present document is focused on the MT-315 silver filled epoxy from Lord, but generic results for other materials were considered in our analysis. Of particular interest was the potential for reducing the bondline thickness to well below the levels currently in use.
Lead Free Solder Paste Testing
Author: James H. Adriance
Abstract: This report contains the results of the phase one lead free solder paste testing. Nine different solder paste vendors supplied two different lots of solder paste for the testing. All tests were conducted on both lots of solder paste. The phase one portion of the lead free solder paste evaluation project included the following tests: solder powder particle size & shape, solder paste metal content, viscosity, slump, solder ball, wetting and surface insulation resistance (SIR).
Drop Testing of Area Array Assemblies Soldered with a Mixture of SAC and SnPb
Author: Brian Roggeman
Abstract: Area array components with lead free solder balls can still be assembled with peak reflow temperatures much below those required for pure lead free assembly by using a eutectic SnPb solder paste. For reasons of thermal cycling performance we have until recently been cautioning against the use of peak temperatures below 240oC but new results suggest that a somewhat lower peak may in fact be acceptable. Strength and fatigue testing at room temperature has already suggested a preference for peak temperatures in the 220-230 °C range. Joints made by mixing 3.8-4.0%Ag SAC balls with eutectic SnPb were tested under relatively mild drop conditions (500-G) to further compare effects of different reflow conditions.
Peak reflow temperatures of 230 °C and 240 °C were compared, and the effects of a second reflow were considered. As is often the case in area array assemblies the weak spot(s) in the present ones were found to be the solder pads rather than the bulk of the solder. Failure generally occurred within the intermetallic layers on the pads, by fracture through the pads or connecting traces, and/or by pad lifting. Lowering the peak temperature was found to delay these failures. An inverted second reflow led to a 30% increase in standoff, which changed the failure mode and appeared to counteract any negative effect of the additional intermetallic formation.
Assemblies were also compared to ones made with the pure SAC alloys. The latter were found to perform considerably better.
Lead Free Solder Paste Print Testing
Author: James H. Adriance
Abstract: This report contains the results of the phase two Lead free solder paste print testing. Phase two testing consisted of squeegee blade and Proflow print testing. This report covers the squeegee blade testing. Nine different solder paste vendors supplied two different lots of solder paste for the testing. The testing was conducted during week 3 of 2006.
Area Array Consortium 2005 Overview
Author: Peter Borgesen
Abstract: The present document offers an executive overview of our 2005 efforts and results. Yielding to popular demand it is much shorter than those of previous years. This was facilitated by the availability of much more in-depth summaries of some of the individual subject areas in other reports. These are referenced in the following.