2004 Reports

Downloads & Resources

Component Underfilling Manual: 2004
Authors: Antonio Prats, Howard Chen and Peter Borgesen
Abstract: Capillary flow driven underfill is a vital part of the flip chip process, improving the reliability of these assemblies. BGAs and CSPs, however, have traditionally achieved good reliability simply through their design and assembly process and have not needed to use underfill. As reliability requirements have increased, more and more manufacturers have become interested in using underfill as a way to meet these new demands.

While this manual borrows heavily from the flip chip-based Underfill Process Manual, there are important differences between underfill for flip chip applications and underfilling packages. The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and troubleshooting. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.

Area Array Rework Quick-Reference
Author: Laurence A. Harvilchuck
Abstract: This guide is designed to be used as a quick reference for senior operators or process engineers who may require assistance when developing a rework process. It contains many features designed to quickly provide the pertinent information. These include:

  • Hyperlinked Table of Contents
    • In the soft version, this takes the reader directly to the appropriate section
  • Process Flow Charts
    • Flow charts are designed to provide the user with a clearer picture of the process flow. Page numbers in the full manual corresponding to the same topic are given on the flow charts.
  • Step-by-Step Walk Through
    • Each step is concisely presented throughout the entire rework process.
  • Tables
    • Process variables and contrasts between tin-lead and no-lead processes are presented in tabular format for simple comprehension.
  • Troubleshooting Guide
    • Symptom-dependent assistance is provided for each phase of the entire rework process to help in quickly isolating the problem and offering a solution

BGA Underfill Method Study
Authors: Howard Chen and Antonio Prats
Abstract: BGA underfill requires review and revision of the criteria normally used for flip chips. Controlling large dispense volumes, dispense pattern selection, multi-pass programming, and throughput optimization are among the first concerns. The effects of material behavior, device warpage, and board designs all need to be carefully investigated and addressed. The project experiments show that BGA can be successfully underfilled using single-edge /multi-pass dispense. The capillary flow material tested, Ablefill 8807, is capable of self-filleting without requiring a close-up dispense. However, the presence of microvias underneath the BGA proved to be a major source of voids.

Partial underfill could be a better alternative, although it requires a material that does not flow in order to avoid contact with solder joints at outmost positions. It allows for a simplified underfill process, less material consumption, and improves access to the solder joints for rework as well. As compared with post-assembly dispense, pre-applied methods seems to provide better location of the underfill under the BGA. Its effect on reliability needs to be verified by the planned mechanical drop test.

Finally, although underfill may help improve the 2nd level reliability of a BGA assembly, it changes the stress state for the whole package. This may affect the 1st level attach inside the BGA package, potentially reducing overall reliability.

QFN / MLF Process Guide: A ‘Cookbook’ for Optimizing Assembly Yield and Reliability
Authors: Michael Meilunas and Ashok Thiyagarajan
The following paper provides detailed design and process guidelines for Quad-flat No-Lead (QFN) packaging based on a substantial body of work performed by the Area Array Consortium. The information presented is designed to supplement and/or supercede the generic guidelines often offered by the device manufacturers. This is especially true for fine pitch (0.4mm) assembly. The goal of this process guide is to improve first pass assembly yields while maintaining or improving the long-term reliability of the QFN devices. Recommendations concerning printed circuit board design, stencil design, and pick and place operations are discussed. The information presented is based on actual experimentation, but due to the many QFN design variations available, it is up to the end user to verify that a good, reliable assembly is achieved before incorporating the recommendations into a final product.

Ball and Polymer Collar Attach to Fine Pitch CSP with the Kester 9690 Flux
Authors: Laurence A. Harvilchuck, Santosh Anil Kudtarkar and K. Srihari
Abstract: Applications of fine pitch Wafer-Level-CSPs (WL-CSPs) may often be effectively limited by their low thermal cycling resistance. One way of improving on this may be to add a ‘polymer collar’ around the base of the solder balls, but that becomes increasingly challenging as the solder ball pitch is reduced. The applicability of an experimental polymer flux material originally developed for BGAs to an 0.5mm pitch WL-CSP was investigated. The achievable collar height was found to be extremely limited. The corresponding reliability is currently under investigation.

Design Overview of Test Features on the Consortium Test Vehicle (CTV-1)
Authors: Wayne T. Jones and Michael Meilunas
Abstract: The CTV-1 is a four (4) layer, 0.062” thick, FR-4 (170o C Tg) laminated, test vehicle designed specifically for use in evaluating assembly robustness and PCB quality. Device attachment and evaluation sites have been added to determine process sensitivity and reliability of various SMT componentry such as fine pitch CSP, BGA, Flip-chip, MLF, passives and wave solderable components. PCB quality is determinable using daisy chained plated-thru-hole (PTH), multi-layer via construction, and surface patterns. The board is OSP finished with Entek Cu-106A, selective nickel/gold over edge tabs and encapsulated with a Probimer 77 solder mask. The design incorporates unique test structures that provide visual, mechanical, electrical and physical evaluation sites, defining data collection and yielding assignment of overall board and assembly performance. Ultimately, the data generated from this test board will provide design, construction, and performance information as well as baseline reliability data for state-of-the-art assembly techniques.

The functional design of this board was developed by Universal Instruments Advanced Process SMT Laboratory as a collaborative of project qualification issues and requests submitted by 2004 Area Array Consortium.

Design Overview of Test Features on the Lead Free Test Board (LFTB-1)
Authors: Wayne T. Jones and Michael Meilunas
Abstract: The Lead Free Test Board (LFTB-1) is a relatively thick (0.093”), multilayer (12 layer), test vehicle designed specifically for use in evaluating robustness and process sensitivity of various laminate and dielectric materials, thru hole and via construction, surface patterns, and State-of-the-Art component attachment sites. The design incorporates unique test structures that provide visual, mechanical, chemical, electrical and physical evaluation sites, defining data collection and yielding assignment of overall board performance. Ultimately, the data generated from this test board will provide design, construction, and performance information as well as baseline reliability data for lead free assembly.

The functional design of this board was developed by Universal Instruments SMT Lab as a collaborative assortment of project specific issues and requests submitted by numerous Area Array 2004 Consortium members with regards to lead free assembly.

Description of Printed Circuit Board TV64
Author: Michael Meilunas
Abstract: The following report describes the design features found on the Area Array Consortium printed circuit board TV64. TV64 is a two layer panel primarily used to construct daisy-chained CSP devices for Pb-free solder alloy studies. TV64 also contains generic footprints of varying pitch for solder joint and component level pull and shear testing and may be used for flip-chip assembly studies.

Effects of Reflow Parameters and Memory on the Microstructure of Lead
Authors: Pericles A. Kondos and Sulakshan V. Mandke
Abstract: SchoolBecause of the fact that intermetallic particles in SAC balls can be very large, the possibility exists that some of them will survive reflow, giving the resulting joint a “memory” of the microstructure of the original ball and inconsistent or unpredictable properties. The present work looked for differences in the microstructure of joints in assemblies made with components that themselves differed in microstructure but were identical in other respects. Ag3Sn platelets were used as a marker of these differences; many combinations of solder alloys and pad metallizations were examined.

Black Pad in Mixed Solder NanoSphere” Assemblies on ENIG Pads
Author: Pericles A. Kondos
Abstract: Microstructure and failure analysis of mixed assemblies made with the Texas Instruments NanoSphere™ Wafer Scale Package on ENIG boards and subjected to torque testing showed that black pad was the exclusive mode of failure in joints with low Pb concentration while it did not appear at all in high-Pb mixed or eutectic Sn/Pb joints, reinforcing the conclusions of older experiments that black pad is a more serious issue in Pb-free assemblies. Only one black pad failure appeared at time zero, before testing began; the rest of the assemblies failed after a considerable number of cycles. Partial black pad cracks were seen in some joints.

Failure Analysis and Microstructure of Mixed Solder NanoSphere” Assemblies
Author: Pericles A. Kondos
Abstract: The microstructure and failure of mixed assemblies with the TI NanoSphere™ WSP on Cu/OSP substrates was studied after these assemblies were subjected to torque testing. The structure of joints reflowed at lower temperatures and low paste Sn/Pb paste volumes was very different for those reflowed at higher temperature or with large amounts of paste. The distribution of cracks as they appeared in cross-sections was studied and correlation between them and the time to failure was sought; there seemed to be little connection. There were big differences in the cracking of the joints that had maximum stresses and the ones right next to them.

Pb-Free Process Guide: First Edition – 2004
Author: Michael Meilunas
Abstract: The following document provides material requirements, inspection guidelines and process recommendations for successful Pb-free area array assembly based upon the experiences of the SMT Process Lab.

This paper is a “living document” and is subject to change as new material sets become available during the transition to Pb-free assembly. The guidelines are focused on common Sn/Ag/Cu alloys such as SAC405 and SAC305 and FR4 printed circuit boards. Currently, only convection oven reflow assembly processes for area array devices are discussed. Wave soldering, pin-in-paste, and other processes guidelines are planned for future revisions.

PCB Materials Damage in Lead Free Assembly
Author: Wayne T. Jones
Abstract: The preponderance of manufacturability and reliability issues surrounding implementation of Lead free assembly in the United States has created a vacuum for knowledge and information. Of specific interest to manufacturability and end-product reliability is the survival of laminate materials used in the production of multi-layer Printed Circuit Boards (PCB’s). This report addresses the impact of Lead free processing on the host of commercially available laminate and dielectric materials used in cost-effective production of PCB’s. Our longer term goal is the development of a comprehensive materials characterization, capability, and usability matrix.

The present report provides an overview of the laminate and prepreg materials included in our investigations, initial materials characterization, and attempts at correlating post-assembly damage with, among other, results of FTIR (ATR), DSC, TGA, and DMA analysis.

Card/PCB Damage in No-Pb Assembly Test Plan
Authors: Wayne T. Jones and Peter Borgesen
Abstract: This document serves to provide goals and objectives associated with evaluation of robustness and process sensitivity of various laminate materials and structures in Pb-free assembly. Test plans that follow are intended:

1) Generate an experimental basis and understanding for proper materials and structure testing protocols.

2) Identify and obtain currently available robust PWB materials and components.

3) Design and build appropriate test board(s) which effectively evaluate material damage at Pb-Free temperatures.

Double Sided No-Lead Assembly: Effect of Component Weight
Author: Pericles A. Kondos
Abstract: In two-sided assembly parts already assembled have only the surface tension of their joints to keep them attached to the board as they go through the second (inverted) reflow. Empirical rules exist for Sn/Pb, but not for lead-free assemblies. An experiment was designed to measure the maximum load that liquid solder joints in an upside-down configuration can carry without breaking, and it was tested with one type of assemblies. Some dependence on the pad metallurgy and alloy composition was seen.

Accelerated Thermal Test Parameters I: Effects of Dwell Time on Pb-free Solder Alloys
Author: Michael Meilunas
Abstract: The following paper describes the results of an experimental procedure used to evaluate the effect of thermal cycle dwell time on the reliability of Pb-free wafer level chip scale packages assembled to multilayered FR4 printed circuit boards. Multiple 0/100oC liquid to liquid thermal shock cycles with in-situ event detection were developed in order to stress the 2nd level interconnections of the surface mount assemblies. The shock cycles evaluated included “symmetric” cycles with dwell times of 15, 30, 120, 280, and 900 seconds at each temperature extreme and “asymmetric” cycles with non-matching dwell times of 30 and 900 seconds. Baseline comparisons were made to Sn/Pb devices subjected to symmetric cycles with 30 and 900 second dwells.

The cumulative Cycle to Failure (CTF) data was analyzed using Weibull distributions and failure analysis was performed on selected samples. The data shows that increasing the dwell time decreases the mean CTF of the Pb-free wafer level CSP assemblies. This suggests that increasing the dwell time allowed more damage to accumulate per cycle in the solder joints resulting in lower lifetime estimates.

An equation was developed using the CTF data in order to predict the necessary dwell time required for maximum damage per cycle, but the results have yet to be confirmed experimentally. The results of the follow-up study will be reported in 2005.

“Alternate Lead Finish QFP Assembly and Lead Pull Study: Includes Sn/Pb, Sn, Sn/Cu, Ni/Pd/Au, & Sn/Bi Lead Finishes”
Authors: Michael Meilunas, Muffadal Mukadam and K. Srihari
Abstract: This report summarizes the lead pull test results for five unique quad flat pack (QFP) component lead finishes. The lead finishes evaluated were tin (Sn), tin-copper (Sn/Cu), nickel-palladium-gold (Ni/Pd/Au), tin-bismuth (Sn/Bi) and tin-lead (Sn/Pb). The QFPs were subjected to pre-assembly steam age conditioning and post-assembly temperature aging prior to the room-temperature pull test. Additionally, pull tests of the Sn/Bi QFPs assembled with Sn/Pb paste were performed at elevated temperature in order to determine if preferential melting phases reduced the pull strength.

Assembly was performed on UIC demo boards. Three 208-leaded .5mm pitch QFP components were assembled on each board. Two solder pastes were used for the assemblies: tin-silver-copper (Sn/Ag/Cu) and tin-lead (Sn/Pb).

The assemblies were characterized by visual inspection, X-ray inspection, and representative cross-sectional analysis prior to the pull test. Microscopic examination of the fracture surfaces was performed following the pull test. Solder void formation, non-wets, and failure mechanisms encountered during the experiment were documented for every QFP and the inspection results were correlated to the pull test data.

This report is an update to “QFP Assembly and Lead Pull Study” and provides the complete pull test results for the entire experiment including that of the Ni/Pd/Au and Sn/Bi finished QFPs and the results for 500 and 1000 hour temperature aging. Please refer to “QFP Assembly and Lead Pull Study” for additional process information, failure analysis, and representative images.

Overall, the results are encouraging. The pull test data indicates that the alternate surface finished QFPs produce solder joints that are as good as or better than the Sn/Pb finished QFPs. Defects were introduced by an 8 hour steam age conditioning, but the occurrence of the defects in the alternately finished QFPs was similar to that observed with the Sn/Pb baseline. Long term temperature aging was shown to significantly decrease the strength of the alternate finished QFP solder joints, but once again, the difference was similar to the Sn/Pb baseline. Furthermore, Sn/Bi finished QFPs assembled with Sn/Pb paste did not produce lower pull forces when testing was performed at elevated temperatures.

Backward Compatible’ Mixed Alloy Reliability
Author: Michael Meilunas
Abstract: All solder alloys are by definition substances containing a mixture of two or more metals. But in the surface mount world, the term “mixed solder alloy” is commonly used to describe solder joints created by mixing Sn/Pb and Pb-free solders during the assembly process.

Mixed solders are complex alloys with three or more constituents. Mixed solders have unique thermal and mechanical properties that may be significantly different than those of the base alloys. These differences may improve or degrade the reliability of the solder joint when compared to a single alloy assembly.

The Area Array Consortium is evaluating mixed Sn/Pb and Pb-free solder alloys in order to better understand how certain controllable factors affect reliability. These factors currently include reflow profile, solder paste volume, and Pb-free alloy composition (example: SAC405 versus SAC305).

The following report summarizes a “mixed” alloy reliability experiment performed by the Area Array Consortium in 2004. Pb-free CSP devices were assembled using varying volumes of Sn/Pb paste in order to create six unique Sn/Ag/Cu/Pb solder alloys with an estimated 2.1 to 8.5 wt% Pb. Three reflow profiles were used for assembly that spanned typical Sn/Pb and Pb-free assembly processes. The completed assemblies were subjected to mechanical deflection and/or air-to-air thermal cycle testing in order to evaluate 2nd level reliability.

Accelerated testing of the experiments concluded in late 2004 and the reliability data was analyzed for this report. The results indicate that the mixed solder alloys are significantly less reliable than “pure” Pb-free alloy. Furthermore, there is a strong correlation between increased Pb% and decreased reliability. Further analysis of the failure mechanisms and solder joint microstructures are planned. Additional reliability experiments are already in progress and the results of these experiments will be reported at a later date.

Assembly and Reliability of Resin Bump CSPs: A Preliminary Evaluation of the Sekisui Micropearl SOL
Author: Michael Meilunas
Abstract: The Sekisui Micropearl SOL is an alternative to traditional flip-chip, CSP, and BGA solder sphere attachments. A Micropearl SOL sphere is a solder plated copper shell containing a resin core that is designed to enhance the thermal cyclic fatigue resistance of area array devices.

The Micropearl SOL is a near drop-in replacement for standard solder bumps and does not require special equipment for product integration although modifications to the PCB and/or device attachment pads may be required for successful implementation.

This report describes an experiment performed with CSP-sized Micropearl SOL spheres. The SOLs were characterized by a variety of techniques including dimensional analysis, cross sectional analysis, and SEM evaluation. The SOLs were then attached to “non-optimized” CSP substrates and assembled to “non-optimized” PCBs in order to evaluate the feasibility of the “drop-in” claim. The SOL assemblies were also subjected to ball shear, mechanical deflection, compression, bend, and thermal cycle testing and the results were compared to devices containing traditional Pb-free solder spheres.

This experiment shows that package and PCB design are vital to the success of SOL integration and that excellent thermal cyclic reliability can be achieved with SOL interconnects. However, advantages and disadvantages were observed when analyzing the mechanical reliability of the SOL assemblies and these factors must be considered before SOLs are incorporated into area array packaging. Additional attachment pad re-design may alleviate some of the mechanical issues encountered and a follow-up study is planned to investigate this idea.

Surface Mount Capacitor Reliability After Lead-Free Assembly
Author: Laurence A. Harvilchuck
Abstract: This exercise evaluates the reliability of surface mount capacitors after experiencing lead-free assembly process conditions. Several capacitor technologies are tested to determine whether these different conditions typically encountered in lead-free assembly processes have any impact on the mechanism of failure and device reliability. The results of three test methods, step stress surge testing (SSST), elevated temperature/humidity aging, and popcorn testing, on the sample set are documented herein.

Overview of 2004 Flip Chip Research
Author: Daniel Blass
Abstract: This report is an overview of the flip chip research conducted in 2004. Each report is discussed briefly along with important results. Much work was conducted on the soldering of gold stud bumped flip chips. A project was conducted on the manufacture of a thin flip chip assembly. While the project was hampered by poor chip carrier quality, the challenges of underfilling large, thin chips were highlighted. Several new fluxes were evaluated with SnPb and Pb-free solder and 10 new underfills were evaluated. The emphasis of reliability testing was on Pb-free assemblies, various thermal cycling conditions, and the effects of aging. Codification and process manuals/cookbooks were updated based on the year’s research.

Area Array Rework Process Manual
Author: Laurence A. Harvilchuck
Abstract: This manual is focused on the rework of area array components, specifically ballgrid array and chip-scale packages, though the techniques described herein may be applicable to other situations (such as flip-chip components). Mechanized or automated rework processes that require the use of a rework station are highlighted throughout, though manual processes are also discussed where relevant to the topic.

Lead-free rework processes will be examined in the context of being an extension of ‘traditional’ tin-lead rework. While the processes are similar, there is the expected divergence in the areas of thermal profiling, site redressing, and reliability. Each of these areas will be addressed in turn throughout this manual.

Rework Thermometry
Authors: Laurence A. Harvilchuck, Zulfikar Malik and K. Srihari
Abstract: When performing the thermal profiling of an assembly prior to rework, the accuracy of the indicated temperature is contingent on both the method and location of the measurement. Several different thermocouple attachment methods and locations were evaluated in this research endeavor to provide a direct comparison of the various options, as well as provide an indication of the thermal profile across the component.

Issues in Thermal Profiling For Lead-Free Rework
Authors: Laurence A. Harvilchuck, Zulfikar Malik and K. Srihari
Abstract: There are numerous small decisions and procedures that can have a significant impact on the thermal profiling and rework processes. The change to lead-free soldering materials has, in many cases, resulted in processes that operate at temperatures much closer to material decomposition points than tin-lead alloy based processes. This exercise closely examines several issues, including station stability, preheating techniques, thermometry equipment, and factors related to forced convection (hot gas) rework. The impact of each of these on a typical lead-free process is quantified, with attention toward best practices in rework.

Effects of Reflow Profile and Aging on the Microstructure of SAC-Soldered Au Joints
Author: Pericles A. Kondos
Abstract: The microstructure of joints formed by soldering Au stud-bumped flip chips on Cu/OSP and ENIG pads using SAC solder paste was studied as a function of reflow profile and paste amount and pretreatment. The dominant phase was seen to depend on the reflow temperature, pad metallurgy, and paste volume, but big variations were seen among joints that had nominally the same values of these parameters. The change in the microstructure caused by long-term storage and high temperature aging was also briefly investigated.

Reflow Encapsulant Manual: 2004
Author: Antonio Prats
Abstract: This is designed as a companion to the Underfill Process Codification. The aim is to present a guide to reflow encapsulant evaluation and process development. The focus here will be to highlight the differences, and to provide some simple and relatively quick characterizations that are necessary for reflow encapsulants. However, this should not be taken to mean that the establishment of a detailed and broad knowledge base is not important. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.

This document will also provide guidance for more detailed tests that will help with process development.

Assembly and Reliability Testing of Soldered Gold Bumped Flip Chips
Author: Daniel Blass
Abstract: This report presents the assembly and reliability work conducted on a process for soldering gold stud bumped flip chips. This process is attractive for low to medium assembly volumes because it avoids the up-front expenses (UBM, masks, redistribution layers, etc.) for solder bumping a small number of wafers. Stud bumped flip chips are dip-fluxed and placed onto solder bumped flip chip pads. The joints are formed during mass reflow and the chip is subsequently underfilled.

The work included a substantial effort to bump substrates for the flip chip assembly. It is expected, however, that production substrates would be bumped by the substrate vendor. The bumping focussed on smaller volumes than used in earlier work. The bumping went smoothly if the stencil apertures were perfectly aligned to the flip chip pads. This, however, is rarely the case since the size of the pads, mask openings, and registration of the mask openings varies from board to board and can vary within a board due to stretch and shrink. Large variations in deposits were observed within flip chip sites depending on the print direction and the alignment to the pad. For a good printing process, tight substrate tolerances would be necessary. With Cu-OSP pads, the solder usually only wets to the top the flip chip pad while the solder completely wets a NiAu pad. For the same solder volume, more solder is available to form joints on the Cu-OSP pad.

A set of non-testable chips was built with 12 reflow profiles with peak temperatures for 233°C to 264°C. The assemblies used various solder volumes and ENIG NiAu and Cu-OSP pad finishes. Some flip chips were placed in wet solder paste while others were assembled by dip fluxing and placing the chip on the reflowed substrate bump. The microstructure of these assemblies were studied as built and after some aging. The microstructure depends on the pad finish, reflow profile, and solder volume.

Testable assemblies were built on substrates bumped with 3x5x12 and 4×12 mil apertures in a 1 mil thick stencil. The pads were formed by 3 mil lines through a 6 to 8 mil thick trench solder mask opening. The substrates were bumped, reflowed, and cleaned before the flip chips were attached with a dip fluxing process. The smaller volume gave assembly defects, electrical opens, with the NiAu pads. Almost all joints soldered but then cracked upon cool down from reflow. After underfill cure, more assemblies failed due to solder joint cracking. This occurred with both solder volumes with NiAu pads and with the smaller solder volume on 62 mil thick Cu-OSP boards. Solder cracking did not cause any failures of chips attached to 16 mil thick Cu-OSP boards.

The chips were underfilled with two underfills with different CTEs. Most assemblies failed by 1000 cycles of liquid shock. With the lower CTE underfill, the assemblies tended to last a bit longer. With much larger solder volumes, failure times with the higher CTE underfill were similar but assemblies with a lower CTE underfill lasted almost 2000 cycles.

Failure analysis found cracks often occurred in or near the substrate pad intermetallic layers. The microstructure evolved with cycling and Kirkendall voids formed next to the gold stud bumps.

Reflow Encapsulant Reliability: Summary of Reports 1995-2004
Author: Antonio Prats
Abstract: This consortium has studied many reflow encapsulants over the years. This document presents a list of the appropriate reports and a summary of the current state of reflow encapsulant reliability performance.

The current best materials include Kester 9101 and 9126, Loctite FF2000 and FF2200. 3M UF3667 has shown good reliability performance; it requires a small (30-100 ms) extra hold time at placement to ensure good assembly. For Pb-free assembly, Kester 9130 has shown mixed performance. Issues regarding substrate outgassing in the high temperature Pb-free profiles must be resolved before any consistent reliability testing can be undertaken.

Air Reflow Experiments with Eutectic SnPb Solder
Author: Daniel Blass
Abstract: The first part of this report discusses air reflow soldering trials with three new flip chip fluxes. These fluxes were used to solder eutectic SnPb bumped flip chips to OSP-coated copper pads. Two fluxes previously found to solder in air were also used. In a short reflow profile with a low soak stage, good soldering was achieved in air with Indium TAC23, Kester TSF-6502, and Multicore M00449 MP200 no-clean tacky fluxes.

The second part of this report examines the effect of pad size on how flip chip joints wetted. Most recent experiments have used relatively small pads, about 3.5 x 7 mil (90 x 175 microns). In several experiments this year, larger pads were used. The length of these pads ranged from about 9 mil (225 micron) to 11 mil (280 microns), with the width being 3 to 4 mil (75 to 100 microns). Such large pads might be needed to compensate for the tolerances on the circuit board features (metal and solder mask) or placement equipment accuracy. When soldering in air, eutectic Sn/Pb solder may fully wet small flip chip pads with the appropriate reflow profile and flux choice. Larger pads, however, may not be fully wetted by the solder unless reflowed in nitrogen. Similar performance on large pads has been found for SnAgCu solders even when reflowed in nitrogen.

Flip Chip Assembly Manual
Authors: Antonio Prats, Peter Borgesen, Daniel Blass, and Pericles Kondos
Abstract: The following presents the framework for a comprehensive manual on the assembly of flip chips onto organic substrates. This manual is intended as a ‘living document’ which will continue to be updated as new knowledge is gained and should be viewed together with existing manuals focused on underfilling of flip chip assemblies and with so-called no-flow encapsulants. At the present stage emphasis is still on eutectic Sn/Pb based assembly, for which our data base and knowledge is by far the most complete, but smaller sections on no-Pb solder and Au stud bumped based assembly will grow considerably over the coming year. Considerable revisions are anticipated over the coming months, based among other on feedback from Consortium principals, and the final format will not be established until the contents are reasonably complete.

Consortium Member Flip Chip/0201 Training Build Report
Authors: Antonio Prats, Daniel Blass
Abstract: The Area Array Consortium has developed an extensive knowledge base about flip chip assembly, which we attempt to pass on to the members in useful ways. A Consortium member was interested in a hands-on technology transfer. Their personnel traveled to UIC to spend four weeks learning about flip chip assembly and performing a complete test board build.

The substrates showed some manufacturing defects, including contamination, solder mask issues, and variations in copper film. The dimensions of substrate features showed variations that were within normal tolerance.

The FP4549 was flowing too quickly on this assembly, trapping a large void under most die. It was replaced by FP4547FC.

Thin Flip Chip BGA Project
Author: Daniel Blass
Abstract: Development work on a thin flip chip BGA package was performed. The device needs to have a low assembled profile for an implantable medical application. Since this is not an application with thermal cycle reliability requirements, the project was issues related to the device assembly process. The package should have low warpage to help achieve a small gap between the BGA and motherboard and still have good assembly yields. Once attached, the BGA may experience multiple thermal excursions during rework cycles and numerous cleaning cycles too.

The work included screening underfills with the cleaning process, help with the substrate design for the test vehicle, arranging for wafer thinning, evaluation of substrates built with several laminates, and a small flip chip build on one substrate type. Quality of the substrates was generally poor but the major problem was with the flatness of the very thin substrates. Room temperature warpage was different on the chip and BGA sides of the carrier. Since subsequent work required different substrates, investigation of warpage at reflow temperatures was not conducted.

Even with a 1-2 mil substrate warpage over the chip sites, assembling a large, thin flip chip was not challenging as long as sufficient solder joint collapse was achieved. Underfilling was more difficult for a variety of reasons, such as the substrate flatness and inconsistent wetting of the underfill to the solder mask. It is harder to avoid getting underfill on top of a very thin chip. Ensuring fillet formation was the biggest problem but this might be addressed with different dispensing equipment.

Pb-Free Flip Chip Flux Evaluation and Wetting of Pb-Free Joints to Large Pads
Author: Daniel Blass
Abstract: Pb-free flip chips were soldered to copper and NiAu pads using 7 no-clean tacky fluxes and nitrogen reflow. Five of the fluxes soldered well. There were differences in how much the Pb-free solder wetted the different sized pads. All of the pads used were formed by traces running into and terminating in a solder mask opening. Small copper pads, about 4 to 6 mils long, were usually completely wetted by the solder. Large copper pads, 9 to 11 mils long, were not completely wetted. The solder would wet down the edges of the pad and wet a short distance out the traces. Reflowing SnPb solder in nitrogen gave complete wetting of the large copper pads but soldering SnPb in air gave wetting similar to the Pb-free in nitrogen.

In one of the SnAgCu flip chip joints on a copper pad, a Cu6Sn5 intermetallic rod was found to protrude out from the side of a joint for a distance of about 10 microns.

Codification Software 2004 Updates
Author: Antonio Prats
Abstract: The ‘Codification Software’ is a decision support / expert system, which serves as a guide (knowledge base) for process and design engineers in the electronics manufacturing industry. It was developed and is maintained by the Area Array Consortium at Universal Instruments. This year the updates include addition of new reliability testing results, and minor updates to the user interface of the Placement Yield software.

Air to Air Cycling (0″C to 100″C) of Pb-free Flip Chips on Thin Substrates
Author: Daniel Blass
Abstract: Flip chips were built on 16 mil thick FR-4 substrates and tested in a one-hour air to air cycle between 0°C and 100°C. The chips were bumped with eutectic SnPb or SnAgCu Pb-free solder. Chips were attached to boards with Cu-OSP or ENIG NiAu pad finishes. The assemblies were fluxed with Kester TSF-6502 no-clean flux and underfilled with Namics U8437-2 or Loctite FP4549.

Chips underfilled with the Namics had very thin exit fillets due to poor self-filleting. In a small number of samples, these thin fillets cracked and allowed underfill delamination. In three assemblies, the corner delamination caused solder joint failure early in cycling. This failure mode was more common in liquid shock testing of similar assemblies. Aside the from corner delamination, no other underfill delamination was observed.

No other electrical failures occurred by the end of testing at 10000 cycles. Cross-sectioning revealed extensive solder cracking in the Pb-free flip chips but the cracking had not yet lead to joint failure. The cracks were located throughout the joint, whereas cracking usually occurs near the chip UBM in liquid shock testing. Few cracks were observed in the eutectic SnPb solder. Some cracking or delamination of the intermetallics from the nickel substrate pad was observed in the assemblies attached to boards with ENIG NiAu pad finish.

Air to Air Cycling (-55″C to 125″C) of SnPb Flip Chips on 31 mil Thick Substrates
Author: Daniel Blass
Abstract: Eutectic SnPb bumped flip chips were built on 31 mil thick FR-4 boards with ENIG NiAu pad finish. The chips were built by dip fluxing with Kester TSF-6502 no-clean tacky flux or by flux jetting Alpha Metals 9171 liquid no-clean flux. The chips were underfilled with Namics U8437-2 with a two-edge L dispense and no close-up pass. Since the underfill did not self-fillet well, the exit edges had very thin fillets.

The flip chip assemblies were subjected to a 70 minute air to air cycle between -55°C and 125°C. The very thin corner fillets cracked during cycling. This allowed underfill delamination and solder joint failure. Nearly half of the samples had failed when testing was halted at 935 cycles. There was also more delamination starting at the solder joints than would normally be observed only after several thousand cycles of liquid shock testing with the same temperature extremes.

Liquid Shock Testing of Pb-free Flip Chips on Thin Substrates
Author: Daniel Blass
Abstract: Liquid shock reliability of Pb-free flip chips built on thin FR-4 substrates has strongly depended on the underfill properties, especially the coefficient of thermal expansion (CTE). Very poor reliability has been observed with underfill CTEs over 45ppm/°C while a CTE of around 26ppm/°C gives comparable performance for thick or thin boards and for SnPb or Pb-free solders.

This experiment tested both Pb-free and eutectic SnPb flip chips on 16 mil thick FR-4 boards with ENIG NiAu and Entek Plus OSP pad finishes. The chips were underfilled with two underfills, Namics U8437-2 (32 ppm/°C) and Loctite FP4549 (45ppm/°C). The assemblies were tested in liquid thermal shock (-55°C to 125°C).

With the higher CTE underfill, all Pb-free assemblies failed by 750 cycles but there was no underfill delamination. With SnPb solder, the assemblies underfilled with FP4549 did not reach 50% failure until 3000 cycles. No solder dependence was found for the Namics underfill. Cracking of very thin edge fillets and subsequent underfill delamination was the primary failure mode with the chips underfill with the Namics underfill. Cross-sections of Pb-free joints were examined with Scanning Electron Microscopy (SEM).

LLTS Results for SnPb Bumped Flip Chips on Immersion Silver Pads
Author: Daniel Blass
Abstract: Eutectic SnPb bumped flip chips were built on boards with two pad finishes, Cu-OSP and Alpha Level immersion silver. The assemblies were built on 31 mil thick FR-4 boards and underfilled with Namics U8437-3. Both sets performed well in liquid thermal shock testing (-55°C to 125°C). Neither set had reached 50% failure by the end of testing at 4500 cycles.

Moisture/Reflow Sensitivity Test Results
Author: Daniel Blass
Abstract: Flip chips were built on thin substrates with two no-clean fluxes and ten underfills. The assemblies were tested to JEDEC Level 3 moisture/reflow classification with a 260°C Pb-free reflow profile. Most chips completely delaminated after the reflows. All underfills popcorned with the eutectic SnPb solder. With Pb-free solder, two underfills had some delamination in some chips but none popcorned. Complete delamination occurred with the rest of the underfills. In most of our testing, underfills have performed better in the 260°C moisture/reflow tests with SnPb solder than with SnAgCu Pb-free.

Underfill Process Manual: 2004
Authors: Antonio Prats, Peter Borgesen, Sandeep Tonapi, Pericles Kondos, Daniel Blass and K. Srihari
Abstract: The capillary flow-driven flip chip underfill process may be taken to include the selection of equipment (dispenser) and material. Creation of the process certainly involves specification of parameters such as bakeout requirements, substrate temperature, needle size, dispense paths (height above the substrate, distance to chip edge, length of pass), dispense rate, needle temperature, volume in each pass, timing of passes, cure parameters. Optimization of the process and specification of the process windows should minimize important variations and account for the inevitable variations (statistics and tolerances).

The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and troubleshooting. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.

The individual sections of this document are carefully organized to minimize the amount of experimental work actually required to reach your goals.

Area Array Consortium 2004 Overview
Author: Peter Borgesen
Abstract: In 2004 one major emphasis of our Area Array Consortium sponsored efforts was on the development and update of process manuals, or ‘cook-books’, guidelines, tools and practical recommendations. Many of the issues underlying these have been researched in considerable depth over the years, and some of our 2004 efforts were aimed at ‘filling in the gaps’.

Otherwise, emphasis was on flip chip technology, no-Pb soldering, mixing of SnPb and no-Pb, and the use of thermal interface materials in fully automated manufacturing. Major new projects were initiated to address two issues associated with no-Pb: Potential damage to printed circuit boards in no-Pb assembly, notably latent damage that may be difficult or impossible to detect immediately, and the occasional degradation of solder pad structures commonly referred to as ‘fragility of SAC joints’ although at least some of the mechanisms are found to occur just as readily with SnPb.

A separate document summarizes our efforts and reports on flip chip, while the present overview briefly outlines the rest.

In-Situ Characterization of Thermal Interface Material Bondlines
Authors: Laurence A. Harvilchuck, Santosh Anil Kudtarkar and K. Srihari
Abstract: One way of reducing thermal interface resistances is to minimize bond line thicknesses, but automated assembly requires careful accounting for manufacturing tolerances as well as process optimization to minimize defects at the boundaries. All of this may well lead to the best and most repeatable overall performance with a trade-off between the bulk thermal conductivity and the processability in realistic configurations of the thermal interface material. Both materials selection and the process optimization therefore require a method for quantitative characterization of performance in realistic assembly. Several methods attempt to estimate the heat flow across the thermal interface using Fourier’s Law and interpolation between the measurement locations. However, few methods gather data at the interface to determine heat flow through the interface regions. In this exposition, we offer a first demonstration of a method that will allow the accurate characterization of the performance of thermal interface material bondlines in actual production test vehicles.

Flow Properties of Thermal Interface Materials
Authors: Laurence A. Harvilchuck, Santosh Anil Kudtarkar and K. Srihari
Abstract: Significant variations in the filler particle distribution of the thermal interface material are observed in the creation of the interface during assembly. These filler particle distributions are believed to be flow induced and both assembly process parameters and materials properties may contribute to this separation.

Framing the Process Window: Improving Thermal Interface Assembly
Authors: Laurence A. Harvilchuck, Santosh Anil Kudtarkar, Zulfikar Malik and K. Srihari
Abstract: Several factors that were perceived to have an impact on the thermal quality of the bond line were taken individually and analyzed for impact on the overall thermal performance of the test vehicle. The magnitude of the impact is discussed, along with insights and observations on other factors that may work in conjunction with the process parameters to alter the thermal performance of the system.