2003 Reports

Downloads & Resources

Evolution of Voids in a Thermal Interface Material During Cure
Authors: Shafi Saiyed, K. Srihari and Peter Borgesen
Abstract: A series of investigative experiments were performed to understand the process variablesthat affect the formation of voids during curing of a common thermal interface material, the Dow Corning 1-4173. Emphasis was on the question of whether it is possible to affect the formation or evolution of voids through the choice of process parameters. The results show the initial heating rate during cure to have clear effects on outgassing and the resulting voids. In general, both placement voids and voids apparently forming during cure grow until the gelling temperature is reached.

Flow Properties of Gap-Filling Thermal Interface Materials
Author: Laurence A. Harvilchuck
Abstract: Ever-increasing amounts of heat are generated in smaller volume packages, producing more stringent requirements on the quality of all thermal interfaces in the system. This necessitates a closer look at the nature of the thermal interface and the impact of process variables on thermal performance. In this first study, the flow properties of gap-filling materials are examined with the prospect of improving uniformity in the applied thermal interface material by varying process parameters.

Heat Sink Attach to PBGA Modules
Author: Thomas R. Homa
Abstract: This report describes work done to determine the requirements of an automated process for attaching heat sinks to PBGA modules with double sided thermal tape. To some extent the present considerations will also apply to attachment to BGAs with metal lids. One major problem using a tape attach is that if one or both surfaces are not perfectly flat large air bubbles are trapped between the module and heat sink, greatly reducing heat transfer efficiency between them. The heat sink was segmented into smaller units to reduce the air entrapment problem. This report will discuss the inaugural efforts to determine if the segmented sink technique will reduce the air entrapment problem. It may also be possible to further improve the transfer from the heat sink by staggering the fin placement.

Printing and Dispensing of Thermal Interface Materials: An Initial Comparison
Authors: Muffadal Mukadam and K. Srihari
Abstract: Frequently, the effects of assembly process parameters are not considered when optimization thermal interface performance. This becomes increasingly critical as demands on this performance continue to grow and alternative processes are developed. Notably, stencil printing is proving to be a competitive alternative to traditional dispensing of thermal interface materials (TIM). The two techniques may, however, pose quite different challenges in terms of material flow, the resulting filler particle distribution, and the risk of air bubble entrapment. The present study offers a discussion and a first case study to identify and illustrate voiding mechanisms for a particular TIM between a heat spreader and the back of a flip chip. Pronounced differences were observed between stencil printing and dispensing in terms of initial void formation, apparently related to specific properties of the material.

Long Term Life of Spliced Optical Fibers Under Static Tensile Loading
Authors: Laurence A. Harvilchuck and Antonio Prats
Abstract: Previous work on ‘pristine’ (as-manufactured) optical fibers led to a considerably improved understanding of accelerated testing including an ability, albeit imperfect, to predict life under a static load. This interpretation of dynamic strength data suggested that the reduced damage rates achievable with a new ‘burst’ stripping technology would allow for much longer life of spliced fibers in service. Quantitative predictions were, however, considered uncertain for two reasons: An incompatibility between sensitivities to humidity in tension and bending shows our mechanistic understanding to still be imperfect, and it cannot be excluded that stripping or splicing introduces minute cracks with different characteristics (as opposed to just larger) than those found in pristine fibers. An ongoing effort addresses this through a comparison of relatively long term life in static bending and tension at various humidity levels to predictions based on dynamic tensile strength data. The present report describes the static tension experiment.

Overview of 2003 Flip Chip Research
Author: Daniel Blass
Abstract: The past year’s research covered many topics in Sn/Pb and lead-free assembly, underfilling, and reliability.

One new project was the assembly of gold stud bumped flip chips. We looked at two assembly processes, reflow soldering to solder bumped substrate pads and bonding with isotropic conductive adhesive. Gold bumps solder easily but the solder joints have a complicated, non-equilibrium microstructure. During thermal excursion, gold diffuses into the solder and solid-state phase transformations occur. Preliminary reliability test results are given. Less was accomplished with conductive adhesives but the results define future process development. Uniformity of the gold bumping process is more important with the conductive adhesive approach than for soldering.

Soldering of eutectic Sn/Pb bumped flip chips in air was investigated with Alpha Level immersion silver and Omikron white tin pad finishes. As with Ni/Au, a wider process window is available with the Alpha silver. Entek Plus and the Omikron tin can be successful with shorter direct-ramp profiles. Flux choice is also important.

Most reflow encapsulant work this year centered on new encapsulants capable of soldering Sn/Ag/Cu bumped flip chips and CSPs. Four materials were investigated. All soldered well with low soaks around 150°C but reflow profiles had to be shortened for soaks a little above 160°C. At lead-free temperatures, outgassing from substrates becomes a serious barrier to the process. Drying the boards with a reflow before assembly can reduce but generally not eliminate voiding. Some of the outgassing appears to be caused by decomposition of the substrate laminate and every excursion to reflow temperature will cause more outgassing. Reliability was not as good as better eutectic Sn/Pb reflow encapsulants. If the assembly and reliability concerns can be resolved, reflow encapsulants offer our best chance at soldering lead-free flip chip in air.

Most underfilling experiments investigated the moisture/reflow sensitivity of various underfill-flux combinations. Eight underfills were tested in combination with three no-clean paste fluxes, as well as five reflow encapsulants. Included in the various experiments were different chip passivation, solder alloy, and bump layout. Large 25mm area array chips with nearly 8000 solder bumps were also tested. The flip chip assemblies were tested to either JEDEC Level 3 or Level 2a with standard or accelerated moisture soaks.

A different underfilling experiment examined underfilling without substrate heating. The encapsulant was dispense along one or two edges of the chip. Depending on the underfill, capillary flow occurred at room temperature or after the assembly was placed into the curing oven. Self-filleting underfills would be preferred for this approach.

Reliability focused on lead-free flip chips, particularly after the chips were thermally aged. The effects varied depending on underfill used, whether the thermal aging occurred before or after underfilling, and the aging conditions. In some cases, aging hurt performance while other cases it appeared to make the joints more thermal shock resistant. One clear result involved using a higher CTE underfill, Loctite FP4549, with lead-free flip chips on thin boards. In liquid shock, the SAC bumped chips failed between 250 and 750 cycles but the Sn/Pb bumped chips lasted thousands of cycles more. In air cycling between 0°C and 100°C, however, both types of assembly have survived more than 5000 cycles without failure. It is not yet known whether the lead-free assembly will perform as well as Sn/Pb in a harsher air thermal cycle.

Along with the aging studies, experiments on the effects of electric current on lead-free joints were conducted. At high current, the microstructure of the joints changed and voids sometimes formed where the current entered the joint. Lower current levels did not change the microstructure and often improved thermal shock performance. This may be similar to the improvements sometimes observed with thermal aging. Microstructure of the lead-free joints was detailed as assembled, after aging or preconditioning, and after thermal shock testing.

A number of process cookbooks are available on this year’s CD. The underfilling process manual was updated with more information specific to underfilling packages. The reflow encapsulant manual updates focus on lead-free soldering. A general flip chip assembly manual is being developed and will be on the final version of this CD. was for underfilling and reflow encapsulant assembly were both updated. There is also a section discussing our currently preferred underfills.

Effects of Pad Finish on Flip Chip Assembly in Air
Author: Antonio Prats
Abstract: While reflow in nitrogen provides the widest process window for flip chip assembly, Sn/Pb flip chips can be soldered in air with a more limited set of fluxes, pad finishes, and reflow profiles.  Several flip chips were assembled onto boards with Alpha Level Ag, Omikron White Sn, Cu-OSP, and Ni/Au pad finishes, with three different fluxes, and five reflow profiles. This data was combined with earlier testing to come up with a general sense of assembly performance.

The current analysis suggests that immAg and ENIG pad finishes are most promising for assembly in air.  It is difficult to solder in SMT-style profiles without nitrogen.  Direct-ramp profiles are more likely to give good soldering

Flip Chip Assembly Manual
Authors: Antonio Prats, Peter Borgesen, Daniel Blass and Pericles Kondos
Abstract: The following presents the framework for a comprehensive manual on the assembly of flip chips onto organic substrates. This manual is intended as a ‘living document’ which will continue to be updated as new knowledge is gained and should be viewed together with existing manuals focused on underfilling of flip chip assemblies and with so-called no-flow encapsulants. At the present stage emphasis is still on eutectic Sn/Pb based assembly, for which our data base and knowledge is by far the most complete, but smaller sections on no-Pb solder and Au stud bumped based assembly will grow considerably over the coming year. Considerable revisions are anticipated over the coming months, based among other on feedback from Consortium principals, and the final format will not be established until the contents are reasonably complete.

Effects of Pad Finish on Flip Chip Assembly in Air
Author: Antonio Prats
Abstract: While reflow in nitrogen provides the widest process window for flip chip assembly, Sn/Pb flip chips can be soldered in air with a more limited set of fluxes, pad finishes, and reflow profiles. Several flip chips were assembled onto boards with Alpha Level Ag, Omikron White Sn, Cu-OSP, and Ni/Au pad finishes, with three different fluxes, and five reflow profiles. This data was combined with earlier testing to come up with a general sense of assembly performance.

The current analysis suggests that immAg and ENIG pad finishes are most promising for assembly in air. It is difficult to solder in SMT-style profiles without nitrogen. Direct-ramp profiles are more likely to give good soldering.

Consortium Flip Chip Builds with Rockwell Automation
Author: Antonio Prats
Abstract: The Area Array Consortium has developed an extensive knowledge base about flip chip assembly, which we attempt to pass on to the members in useful ways. Rockwell Automation was interested in a hands-on technology transfer. Rockwell personnel traveled to UIC for one flip chip build, and then UIC personnel traveled to Rockwell for a repeat build at their site. This exchange allowed both parties to learn many subtle things about flip chip assembly process development that are not necessarily obvious.

Effect of Electric Current on Lead-Free Flip Chips
Author: Pericles A. Kondos
Abstract: The effects of sending strong electric current through lead-free flip chip joints for extended periods was studied. It was found that when the current was strong enough, extensive electromigration of the various intermetallics inside the joints took place, occasionally accompanied by void formation. Less strong currents did not produce visible changes in the microstructure of the joints, but had an effect on their reliability. It was not clear if this effect was exclusively due to thermal aging as a result of the heating of the joints by the electric current, or if electromigration had an extra contribution to it.

Assembly of Gold Stud Bumped Flip Chips with Isotropic Conductive Adhesives
Author: Daniel Blass
Abstract: This report discusses some initial progress on the assembly of gold stud bumped flip chips with isotropic conductive adhesives. A viable process has not yet been developed but there are a number of useful conclusions that help define the future work.

Based on these experiments, bump height is an important variable to the success of this process. If the bump heights vary more than a few microns, coining the bumps during dipping and placement will be helpful. If equipment limitations prevent using enough force, coining prior to assembly is possible too. Co-planarity of the chip and coining surface will be important. During placement, however, co-planarity of the chip to substrate is less important as the long as each bump is coined against its corresponding substrate pad.

Robustness of the adhesive joints formed by dipping was not promising. Cracking or delamination of the adhesive occurred between curing of the joint and curing the underfill. Coining on placement may help form a larger bond area with the substrate pad. It may be possible to improve adhesive transfer during the dipping process. Along with the viscosity and wetting properties of the adhesive, how long the bumps sit in the adhesive and how quickly the bumps are removed from the adhesive will affect how much adhesive remains on the bumps after dipping. A faster dipping process than employed here, a 500ms dwell in the adhesive, would be preferred for better throughput. Placing in printed adhesive will give a larger adhesive bond but will be limited to larger pitches and would not be preferred if solder paste also needs to be printed onto the substrate.

Tolerances on the bump location are typically ±5mm but were larger in the samples examined. Placement equipment accuracy is also more important for adhesive assembly because, unlike solder, there is no self-alignment.

Evaluation of Gold Stud Bumping
Author: Daniel Blass
Abstract: This report discusses the gold stud bumping on the test chips used in this years work and the results of coining experiments. Chips were bumped by two sources. Bump size and shape varied.

The height of more than 39000 bumps were measured using a Wyko white light interferometry system. In contrast to spherical solder bumps, this system has difficulty measuring uncoined stud bumps. The top most peak of the bump may not reflect too few pixels. While operator intervention could fine tune the measurement, this was not optimal for this many measurements. Due to measurement error, some bumps may actually be taller than measured but not shorter.

In a few cases, low bump height variation of less than 10 microns across chip was obtained. Larger variations of 20 to 40 microns were more common. The largest variations were typically caused by long tails on the bumps. These tails could be coined to produce very low variation across a chip. Planarity between the chip and coining tool is critical for achieving small variations. Coining forces as low as 27g per bump gave height variation of just 1.3mm across a 37 bump chip.

In the large set of uncoined bumps, a few bumps were shorter than the coined bumps but the uncoined data may not be accurate. For a process such as dipping in adhesive, however, short bumps will lead to poor assembly yields. It will be important to develop accurate methods to measure gold stud bumps and develop statistics on the shortest bumps.

Soldering Gold Stud Bumped Flip Chips
Author: Daniel Blass
Abstract: This report discusses the assembly of gold stud bumped flip chips with solder. Both lead-free and eutectic SnPb solders were used. Flip chips were assembled by dipping the gold bumps into a thin film of no-clean tacky flux and placing the chip onto the solder-bumped substrates. With sufficient solder, assembly was successful. A small number of flip chips built with SnAgCu solder on copper pads were subjected to liquid thermal shock testing. With a low CTE underfill (26ppm/°C), first failure occurred after 1625 cycles and a second failure occurred by 2000 cycles. With a high CTE underfill (45ppm/°C), the chips failed between 375 and 750 cycles.

The substrates had solder applied to the flip chip pads before the flip chip was attached. One substrate had SnCu solder applied by the substrate vendor but the amount of solder was not enough to overcome the gold bump height variations. Joints that did form cracked between assembly and underfilling. When solder paste was printed on these substrates to increase the solder volume, the paste deposits often did not coalesce with the existing SnCu solder. This indicated a solderability problem with the solder on the pads.

The other test vehicles had solder applied by stencil printing type 5 or type 6 solder paste onto the flip chip pads and reflowing the substrate. One substrate with Cu-OSP pads was bumped with SnAgCu solder. For another test vehicle, substrates with Ni/Au and Cu-OSP pads were bumped with eutectic SnPb solder. Because the pad size differed, less SnPb solder paste was printed than SnAgCu. Due to the complex metallurgy of joints with high gold composition, the amount of solder will be a critical variable. Further study needs to address the solder joint microstructure, how it affects reliability, and how the microstructure changes with thermal cycling and thermal aging.

The Microstructure of Tin-Silver-Copper Flip Chip Joints and Its Evolution
Author: Pericles A. Kondos
Abstract: The microstructure of LF2 bumps on PB8 die, as well as of assemblies with these die on substrates with Cu/OSP and Ni/Au pads, was studied in detail, mostly by observation of cross-sections in a SEM. The microstructure was altered by various thermal treatments, including multiple reflows and thermal aging; further changes to it were caused by LLTS cycling. Particular attention was paid to the intermetallics growing on the two pads, as well as to the number and distribution of the large Ag3Sn and Cu6Sn5 intermetallics forming inside the joints. The behavior of these intermetallics was not the same for the two pad finishes, but what effect the differences had on the reliability of the joints is not clear. The paths followed by the cracks that formed during LLTS were examined, with an eye on whether they were affected by the presence of Ag3Sn platelets nearby. The ultimate purpose of this study was to see which factors affected the reliability and how these factors could be influenced by the choice of assembly conditions. Some trends regarding the various intermetallics have indeed emerged, but their effect on the reliability is not clear as yet.

Assembly Evaluation of Kester 9126 Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari
Abstract: Kester SE-CURE 9126 is a reflow encapsulant designed for eutectic Sn/Pb flip chip assembly. With the default placement settings, there were no placement related defects such as die shifting or floating with a 5mm flip chip. It exhibited good soldering with reflow profiles that have low soak temperatures (150°C) or in direct-ramp profiles. Reflow profiles with higher soak temperatures (over 165°C) gave soldering defects because the encapsulant started to cure before solder joints formed. This limitation makes Kester SE-CURE 9126 less attractive to assemble components that will see higher temperatures during reflow. No underfill voids were observed in acoustic microscope images.

Assembly Evaluation of a Kester SE-CURE 9130 Reflow Encapsulant for Pb-Free Flip Chip Assembly
Authors: Ji Hyon Mun and K. Srihari
Abstract: Kester SE-CURE 9130 is a reflow encapsulant designed for Sn/Ag/Cu bumped flip chips. The encapsulant was evaluated by assembling LF-2 bumped PB8 flip chips. The LF-2 solder composition is 95.5% Sn, 3.5% Ag, and 1.0% Cu. Placement parameters and soldering in various reflow profiles were evaluated.

This encapsulant gave good soldering with reflow profiles with 150°C soaks that took up to 4.5 minutes to reach peak temperature. With a 165°C soak temperature, poor soldering was observed for profiles that took 4 minutes to peak temperature but shorter profiles did solder. Direct-ramp profiles that reached peak temperature in 2.5 minutes soldered well while profiles that reached peak in 3.5 minutes did not solder well. All cases of poor soldering was caused by gelling and curing of the encapsulant before the solder joints could form.

Default placement parameters were adequate for placing the 5mm PB8 chip without having the die shifting off the pads. Larger components may need higher force or additional hold time to prevent shifting after the component is placed.

Assembly Evaluation of 3M UF3667 Reflow Encapsulant
Author: Antonio Prats
Abstract: 3M UF3667 is a reflow encapsulant designed for eutectic Sn/Pb assembly. It was evaluated with various dispense amounts, placement parameters, and two reflow profiles.

There were no reflow profile-related defects. Assemblies made with the default placement parameters of 150 g of force and 30 ms of hold time were often found to have shifted during reflow. 65 and 100 ms of hold time were used with no placement related defects. While these hold times are still faster than the time used for dip fluxing, other reflow encapsulant materials can be used with the default 30 ms.

A two hours bakeout at 125°C was insufficient to prevent voiding in the assemblies. The addition of one pass through the reflow oven after this bakeout reduced voiding significantly.

Evaluation of Reflow Encapsulants for Pb-Free Flip Chip
Authors: Antonio Prats, Sunil Gopakumar and K. Srihari
Abstract: This report discusses the assembly evaluations of four reflow encapsulants that are designed to solder with the Sn/Ag/Cu alloy; Loctite CNB933-03, Emerson and Cuming A and B, and Kester 9130. Flip chip assemblies were built to study the effects of various process conditions on assembly, and compatibility with the Surface Mount Technology (SMT) process. The first experiment studied the assembly characteristics of the four materials with respect to placement hold time, placement force, bakeout conditions, reflow profiles. The second study considered various bakeout conditions required to reduce voiding in the assemblies. The third build was performed to create samples for reliability testing.

None of these materials require any extra placement force or hold time.

All of these materials performed well in the low soak and short higher soak reflow profiles that were tested. The most difficult profiles are those with more heat input before peak temperature.

Voiding seems to be the major issue for reflow encapsulants. There was significantly more voiding seen when soldering SAC solder than Sn/Pb. This may be due to some processing differences between the solder bumps. These differences, however, are to be expected, and an ideal encapsulant will be able to handle of either solder bump type. Passing the board through a Pb-free reflow profile in addition to the standard bakeout was seen to reduce voiding.

There is also a slight preference for assemblies soldered to Ni/Au pad finish versus Cu-OSP. It is not clear whether this difference is due to the pad finish itself or some complex interaction between the solder, pad finish, flux residue, and encapsulant.

Reflow Encapsulant Manual: 2003
Author: Antonio Prats
Abstract: This is designed as a companion to the Underfill Process Codification. The aim is to present a guide to reflow encapsulant evaluation and process development. The focus here will be to highlight the differences, and to provide some simple and relatively quick characterizations that are necessary for reflow encapsulants. However, this should not be taken to mean that the establishment of a detailed and broad knowledge base is not important. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.

This document will also provide guidance for more detailed tests that will help with process development.

Effect of Thermal Aging on Sumitomo CRP-4152R5 Underfilled Lead-Free Flip Chips
Author: Pericles A. Kondos
Abstract: Assemblies with LF2-bumped PB8 die on 16 mil thick FR-4 boards with Cu/OSP and Ni/Au pad finishes, underfilled with Sumitomo CRP-4152R5, were aged for 75h at 125ºC and their reliability was compared with that of non-aged assemblies by subjecting both to LLTS. It was found that assemblies on Cu/OSP pads had a dramatic improvement in reliability, while assemblies on Ni/Au had a smaller but still significant improvement. An extensive study of the microstructure of the joints before and after aging and/or cycling was performed, in order to see if the change in reliability could be connected with changes in the microstructure.

Effect of High Temperature Reflows on the Thermal Shock Performance of Sn-Ag-Cu Bumped Flip Chips
Authors: Sunil Gopakumar and K. Srihari
Abstract: Variations in the peak reflow temperatures for lead-free flip chip assembly could change the microstructure and composition of the solder joints. These changes could affect the mechanical properties and fatigue resistance of the solder joints. While a previous experiment had shown a strong reliability reduction with a hotter reflow profile, this experiment found similar thermal shock performance for Sn/Ag/Cu bumped flip chips attached with reflow profiles that had peak temperatures of 250°C, 260°C, and 270°C. The higher reflow temperatures did not give very early failure in cycling.

Effect of Thermal Aging on Sn-Ag-Cu Bumped Flip Chips Underfilled with Loctite FP4549
Authors: Sunil Gopakumar and K. Srihari
Abstract: This research focused on the impact of thermal aging on the thermal shock performance of SAC flip chips on thin FR-4 substrates. SAC bumped flip chips assembled on Cu-OSP and Ni/Au pads were thermally aged before or after underfilling and then subjected to thermal shock. Loctite FP4549 was used to underfill the flip chips.

All assemblies, even those that were not aged, failed quickly in thermal shock compared to similar assemblies on this board thickness with other underfills, or with this underfill on thicker boards.

Aging for 75 hours at 125°C or 150°C significantly reduced lifetimes compared to no aging. This occurred for both Ni/Au and Cu-OSP pad finishes. Flip chips attached to Cu-OSP pads were aged after underfilling for 75 hours at 75°C, 100°C, 125°C, or 150°C. Compared to the non-aged sample, the results were only marginally significant for the lowest temperature. Among the four temperatures used to aged chips after underfilling, however, there was a trend for lifetimes to increase with the aging temperature.

Effect of Thermal Aging on Air Thermal Cycling Results for Non-Underfilled SAC Bumped Flip Chips
Authors: Sunil Gopakumar and K. Srihari
Abstract: In this experiment, SAC bumped flip chips were attached to thin FR-4 substrates and then aged for 75 hours at 125°C or 150°C. The chips were not underfilled. The assemblies were subjected to air thermal cycling between 0°C and 100°C. Because of the small solder joints and large distance to neutral point for the 5mm chip, all failures occurred by 68 cycles.

On Cu-OSP pads, aging at 125°C reduced lifetime but aging at 150°C produced a slight but not significant improvement. On Ni/Au pads, both aging conditions gave longer lifetimes but the difference was not significant for aging at 125°C. At all three conditions, chips attached to Cu-OSP pads lasted significantly longer.

Effect of Thermal Aging on Solder Joint Shear Strength and Thermal Shock Performance of Sn-Ag-Cu Bumped Flip Chips
Authors: Sunil Gopakumar and K. Srihari
Abstract: Aging of Sn/Ag/Cu bumped flip chips was examined. Chips were aged up to 1000 hours at 125°C and up to 220 hours at 150°C. After aging, half of the chips were sheared off to measure the strength of the solder joint. The remaining chips were underfilled and tested in liquid thermal shock.

For up to 1000 hours at 125°C, more aging decreased shear strength of Sn/Ag/Cu solder joints on Ni/Au and Cu-OSP pads. The effect of aging at 150°C was more complicated. Shear strength dropped off after 30 hours but then increased after about 75 hours and then dropped again after 220 hours at 150°C.

Aging at either temperature did not produce any clear effects on liquid thermal shock performance. There were some early failures for chips aged between 15 or 30 hours at 150°C. While Cu-OSP pads usually give better reliability, this pad finish gave more failure among the aged at 125°C.

High Temperature Moisture / Reflow Sensitivity Testing of Area Array Flip Chip Assemblies
Author: Daniel Blass
Abstract: This experiment tested moisture / reflow sensitivity of a number of underfills and fluxes with 5mm and 25mm area array FA10 chips with a 10 mil bump pitch. No-flow or reflow encapsulants were also used with the 5mm flip chips. Testing was performed to JEDEC Level 3 with an alternative moisture soak of 40 hours at 60°C/60%R.H. The peak reflow temperature was 260°C.

No-flow underfills gave no delamination but solder extrusion into underfill voids were common. Voiding issues must be addressed before these materials are relevant for area array chips.

The capillary flow underfills were more likely to delaminate but the delamination was often limited to small areas. The experimental Loctite CNB944-15 gave popcorn delamination for two of the 5mm chips and all of the 25mm chips. Loctite FP4547FC had small areas of delamination in both large and small chips. Namics U8437-2 had a small area of delamination in one 5mm chip but popcorned in the 25mm chip. Loctite FP4549 and Namics U8437-3 gave no delamination in the small chips but a large solder extrusion was found in one chip with Loctite FP4549. Further reliability testing is needed to see whether the small areas of delamination are acceptable.

High Temperature Moisture / Reflow Sensitivity Testing of Flip Chip Assemblies
Author: Daniel Blass
Abstract: Underfill-flux combinations were subjected to the JEDEC moisture / reflow sensitivity testing. Testing was performed at Level 3 with a standard and accelerated moisture soak and at Level 2a with an accelerated soak. The chips were bumped with SnPb or SnAgCu solder and had either a nitride or a BCB passivation. Chips were attached to thin FR-4 substrates with Cu-OSP pad finish.

As with previous experiments, the eutectic SnPb solder usually performs better than the SAC solder if the chip has a nitride passivation. Underfills performed better with the SAC solder if passivation was BCB instead of nitride. Polyimide passivation layers would perhaps also give better results. More underfills performed poorly with the Indium TAC23 flux and more underfills performed better with the Kester TSF-6502.

In many cases, the delamination observed was only one or two small areas near the solder joints. While no delamination is preferred, these may still give acceptable results in thermal cycling. Some chips had large areas of delamination that are more serious reliability and assembly risks. Only a few underfill-flux combinations gave complete delamination or the loss of solder into underfill cracks or delaminated interfaces.

Liquid Thermal Shock Testing of Pb-Free Flip Chips Built with Kester 9130 Reflow Encapsulant
Authors: Ji Hyon Mun and K. Srihari
Abstract: This report investigates the reliability performance of the Kester SE-CURE 9130 reflow encapsulant. This encapsulant is capable of soldering Pb-free Sn/Ag/Cu bumped flip chips. Flip chips bumped with Sn/Ag/Cu and the eutectic Sn/Pb solders were attached to thin FR-4 circuit boards with Cu-OSP and Ni/Au pads. The flip chip assemblies were subjected to 2000 cycles of liquid thermal shock testing.

Failure times for all combinations of solder alloy and pad finish were comparable. For both pad finishes, the Sn/Ag/Cu bumped flip chip assemblies had no failures at 1000 cycles, 50% to 55% failure after 1500 cycles, and more than 80% failure after 2000 cycles. The same results were observed for Sn/Pb solder on OSP pad. For the 10 Sn/Pb bumped chips attached to Ni/Au pads, one chip failed by 1000 cycles, three after 1500 cycles and 9 of 10 failed by 2000 cycles.

Few chips showed underfill delamination and those that did have delamination had only small areas of delamination by 2000 cycles, either at the chip corners or along the perimeter solder joints. Many chips failed without observable delamination.

A bakeout condition of 2 hours at 125°C was not sufficient to prevent underfill voids from forming during assembly. Drying with one or more reflow passes did not give voiding in a previous experiment.

Reliability Testing of Sn/Pb Bumped Flip Chips Built With Reflow Encapsulants
Authors: Daniel Blass, Ji Hyon Mun and K. Srihari
Abstract: Eutectic Sn/Pb flip chip assemblies were built with four reflow encapsulants on thin FR-4 substrates with Cu-OSP pad finish. One set was cycled without any preconditioning while a second set were first preconditioned with the JEDEC Level 3 moisture/reflow test with a peak temperature of 260°C. All assemblies passed the precondition with no underfill delamination. The assemblies were then subjected to 2000 cycles of liquid to liquid thermal shock between -55°C and 125°C.

The best performers in LLTS depended on whether the parts were preconditioned. Without preconditioning, the Kester 9126 was the best followed by Loctite FF2200, Kester 9101 and an experimental material from Indium. With preconditioning, Kester 9126 and the Loctite FF2000 failed faster than the other two materials. The preconditioning had little affect on the failure times of Kester 9101 and the Indium material. Failures occurred between 1000 and 2000 cycles.

Encapsulant volume was included as a variable for three encapsulants but there was not a consistent trend for all combinations. This result may be due to competing failure mechanisms.
With reflow encapsulants, chips often fail without delamination. No delamination was observed in any chips with the Kester 9126. Kester 9101 had the most delamination. A few chips built with the Indium encapsulants had delamination similar to the 9101. The Loctite encapsulant had small areas of delamination by 2000 cycles.

Thermal Shock Performance of Sn-Ag-Cu and Sn/Pb Bumped Flip Chips Aged for 100 Hours at 150″C
Authors: Sunil Gopakumar and K. Srihari
Abstract: This report investigates the thermal shock performance of flip chips aged for 100 hours at 150°C. Chips bumped with Sn-Ag-Cu and eutectic Sn/Pb solders were attached to circuit boards with Ni/Au and Cu-OSP pad finishes. The flip chips were underfilled after the aging step with Sumitomo CRP-4152R5.

The aging strongly reduced lifetimes in thermal shock for both solders. For the lead-free solder, all aged chips failed by 1000 cycles on Ni/Au pads and by 1500 cycles on Cu-OSP pads. By 3000 cycles, however, the non-aged lead-free assemblies had just 14% failure on Cu-OSP pads and 43% failure on Ni/Au pads. For Sn/Pb solder, none of the non-aged assemblies failed by 3000 cycles. With aging, the first Sn/Pb failure on Ni/Au pads occurred by 1000 cycles and half had failed by 2000 cycles. On Cu-OSP pads, the first aged assembly failed after 2000 cycles and half had failed by 2500 cycles.

While there were obvious differences in lifetimes, cross-sections of aged and non-aged lead-free joints did not show obvious differences in microstructure or crack growth. Prior to thermal shock testing, the thermal aged samples did undergo coarsening of the microstructure. Thermal shock testing, however, had much greater effect on the microstructure and the aged and non-aged looked similar after cycling.

Thermal Shock Testing of Two Reflow Encapsulants for Pb-Free Flip Chip
Authors: Sunil Gopakumar and K. Srihari
Abstract: Two lead-free reflow encapsulants were used to assemble Sn/Ag/Cu and eutectic Sn/Pb bumped flip chips. The encapsulants were Kester SE-CURE 9130 and Loctite CNB933-03, an experimental material. Previous work had evaluated the soldering performance of these materials in various reflow profiles.

Chips built with Loctite CNB933-03 all failed by 250 cycles of liquid to liquid thermal shock testing. These chips had not received a post-reflow cure step that Loctite suggested might improve reliability. Chips built with Kester 9130 lasted longer but still had many failures by 1000 cycles. In a previous experiment with the same assembly conditions, there were no failures with the Kester 9130 by 1000 cycles.

Room Temperature Underfilling With A Capillary Flow Material
Authors: Muffadal Mukadam and K. Srihari
Abstract: Traditional capillary underfilling of an area array component involves heating the substrate so as to reduce underfill viscosity and aid wetting and flow under the die. However, it would obviously be attractive to eliminate this requirement. Notably, this would contribute greatly to making stencil printing a viable alternative to underfill dispensing. Potential obstacles would include incomplete underfilling or exit fillet formation, as well as reduced wetting and thus enhanced voiding under the chip. A preliminary study addressed some of the issues for 5-14mm perimeter and area array die by varying underfill material, initial distribution along the die edge, and the final cure profile. For different reasons two of the otherwise currently preferred materials do not seem generally suited for room temperature underfilling, but a material with appropriately selected intermediary wetting properties might be expected to work better.

Underfill Process Manual: 2003
Authors: Antonio Prats, Peter Borgesen, Sandeep Tonapi, Pericles Kondos, Daniel Blass and K. Srihari
Abstract: The capillary flow-driven flip chip underfill process may be taken to include the selection of equipment (dispenser) and material. Creation of the process certainly involves specification of parameters such as bakeout requirements, substrate temperature, needle size, dispense paths (height above the substrate, distance to chip edge, length of pass), dispense rate, needle temperature, volume in each pass, timing of passes, cure parameters. Optimization of the process and specification of the process windows should minimize important variations and account for the inevitable variations (statistics and tolerances).

The present document offers an attempt at a step-by-step approach to the development of such processes: Preparatory work, rapid development of a process for a given application, and troubleshooting. The establishment of a sizeable knowledge base is strongly recommended, through work done by your materials and equipment suppliers, as well as by yourself during final qualification or the development of processes for individual applications.

The individual sections of this document are carefully organized to minimize the amount of experimental work actually required to reach your goals.

Assembly of 0.4 mm Pitch Wafer Level Chip Scale Packages (WLCSPs)
Authors: Muffadal Mukadam and K. Srihari
Abstract: The present report describes the results of systematic work to develop a robust solder paste printing process for assembly of 0.4mm Wafer Level CSPs together with other, larger pitch components. Parameters considered include stencil thickness, aperture size and shape, print parameters (squeegee angle) and approach (enclosed printhead vs. squeegee), stencil cleaning, solder paste type and brand. Recommendations are made for printing through 4 and 5 mil thick stencils with a minimum of statistical scatter and defects.

Flux Bridging During Fine Pitch Stencil Printing
Authors: Muffadal Mukadam and K. Srihari
Abstract: Work reported elsewhere suggests that the use of an enclosed printhead may allow for a wider solder paste printing process window for fine pitch components than squeegee printing because it offers a better shape of the individual print deposits. However the approach is more likely to force particle-flux separation and flux bleed-out, leading to paste compaction in the chamber and the potential for flux bridging which then tends to cause solder bridging in subsequent reflow. The present report addresses flux bridging problems observed during fine pitch stencil printing of solder paste using the DEK ProFlow enclosed printhead.

Flux-Only Assembly and Reliability of 0.4mm Pitch Wafer-Level Chip Scale Packages
Authors: Laurence A. Harvilchuck and Muffadal Mukadam
Abstract: This study details the assembly and reliability of 0.4mm wafer level chip scale packages (WLCSPs) attached to electroless nickel immersion gold (ENIG) coated substrate pads without the use of solder paste. Both eutectic tin-lead (SnPb) and tin-silver-copper (LF2) bumped components were considered. The devices were flux-dipped prior to placement, and subsequently reflowed under nitrogen. Life in air-air thermal cycling (AATC) was compared to the failure distributions achieved on OSP-coated copper pads with solder paste printing.

Mixed BGA Assembly A Build Utilizing Sn/Pb and Pb-Free Solder Alloys
Author: Michael Meilunas
Abstract: Universal Instruments’ Consortium Test Board 6 side C (TB6-C) was designed to evaluate assembly and reliability issues associated with daisy-chained 1.27mm pitch, 256 I/O plastic ball grid array (PBGA) devices.

In mid 2003 TB6-C was utilized to study the effects of “mixed” BGA assemblies, or assemblies created using a combination of eutectic Sn/Pb and Pb-free solder alloys. In order to complete the build, identical BGA devices were obtained with Sn/Pb, Sn/Ag/Cu and Sn/Ag solder spheres. These devices were then assembled with Sn/Pb and/or Sn/Ag/Cu solder pastes to copper OSP or Sn/Pb HASL finished printed circuit boards (PCBs). An additional BGA device with Sn/Ag/Cu solder bumps was also assembled in a similar manner and was used to study the effects of double sided assembly under mixed conditions.

Three “realistic” reflow profiles were developed to simulate possible assembly scenarios. The three profiles were:

1. Low end Sn/Pb reflow with a peak temperature of 205 to 211oC across the PCB. This profile may be encountered in eutectic Sn/Pb assembly and mixed assembly utilizing Pb-free devices and Sn/Pb paste. The peak temperature does not exceed the reflow temperature of the Pb-free alloys.

2. Standard to upper end Sn/Pb reflow with a peak temperature of 221 to 228oC across the PCB. This profile may be encountered in eutectic Sn/Pb assembly and mixed assembly utilizing Pb-free devices and Sn/Pb paste. The peak temperature barely exceeds the reflow temperature of the Pb-free alloys.

3. Standard Pb-free reflow with a peak temperature of 240 to 245oC across the PCB. This profile may be encountered in pure Pb-free assembly and mixed assembly utilizing a combination of Pb-free paste, Pb-free devices, Sn/Pb paste, and/or Sn/Pb devices. The peak temperature of this profile sufficiently exceeds the reflow temperature of the Pb-free alloys.

The build also addressed the feasibility of double sided mixed assembly by assembling Pb-free devices with Sn/Pb paste for all three reflow conditions. The assemblies were then flipped and passed through the reflow oven for a second reflow pass. These assemblies were then compared to Pb-free devices assembled with flux or Sn/Ag/Cu solder paste using the Pb-free reflow profile and a second reflow pass.

The following report describes the test board design, component construction, and solder alloys pertinent to the builds. Assembly details including basic stencil and printer information and reflow profiles are included. Post-assembly inspection and analysis may also be found in this report as well as a brief description of the tests that are to be performed on the TB6-C BGA assemblies.

The build has shown that mixed alloy solder joints can be successfully assembled under the conditions evaluated. No complications or defects were associated with the inverted reflow pass. The BGA assemblies are currently in 0/100oC air to air thermal cycling in order to evaluate the reliability of the 2nd level solder joints.

CSPTB8-B Consortium Build at Rockwell Automation
Authors: Muffadal Mukadam and K. Srihari
Abstract: This report summarizes the details of an assembly build that was performed at Rockwell Automation (at Cleveland, OH). The assembly build was designed to assemble various area array components ranging from 1.27 mm pitch Ball Grid Array (BGA) packages, 0.8 mm pitch Chip Scale Packages (CSPs), and 0.5 mm pitch Thin Quad Flat No-Lead (TQFN) packages, to 0.5 mm and 0.4 mm pitch Ultra CSPs. The objective of the build was to establish a stable paste printing process for the 0.4 mm pitch Ultra CSPs.

The assemblies were performed on Test Board 8 side B (CSPTB-8). A type 3 Indium SMQ 92J eutectic Sn/37Pb solder paste with 90.5% metal content was used for the assemblies. A 10” MPM Rheopump was utilized for stencil printing, a Universal GSM was used for component placement, and a 7 zone BTU Paragon forced convection oven was utilized for reflow soldering.

Printing and assembly experiments performed at UIC showed positive results. However, at Rockwell substantial paste volume variation was observed between the 0.4 mm pitch WLCSP board sites. This variation was attributed to board bending within the stencil printer. Also, considerable paste volume variation was observed between the forward and the backward stroke directions. Solder bridging was observed more frequently in a particular stroke direction than in the other.

It is expected that the two printing systems (i.e. ProFlow and Rheopump) would give similar performance if tested under similar conditions. In this particular case, a difference in board support may be the primary culprit for an unstable process with the Rheopump. The following report provides all materials related information with regards to the test board, components, solder paste, and stencil. Assembly details including stencil printer settings, pick and place operations, and reflow profiles are also delineated. The report also covers a brief introduction to enclosed printhead printing, the stencil printing issues that were faced during the build, and the assembly results.

Solder Bridging in Assembly of 0.4 mm Pitch WLCSPs
Authors: Shafi Saiyed, Muffadal Mukadam and K. Srihari
Abstract: This report discusses the concern of solder bridging during the assembly of 0.4 mm pitch WLCSPs. A methodological approach was adopted to understand the occurrence of solder bridging. There were no occurrences of solder bridging after stencil printing. However, the higher volume of paste deposited during printing and subsequent squeezing of the paste and/or flux during component placement results in separation of solder paste particles. The separated solder paste particles can potentially cause solder bridging.

“Test Board 8B Build Documentation A Build Involving Mixed Alloy, TQFN, and .4mm Pitch CSP Assembly”
Authors: Michael Meilunas and Mark Dunlap
Abstract: Universal Instruments’ Consortium Test Board 8 revision B side B (TB8B-B) was designed to evaluate assembly and reliability issues associated with daisy chained 1.27mm pitch BGA devices, 0.8mm pitch CSPs, 0.5mm pitch TQFNs, 0.5mm Ultra CSPs, 0.5mm pitch CSPs and 0.4mm pitch Ultra CSPs.

An assembly build was performed in March 2003 using 30 TB8B-B with copper OSP surface finish. Eutectic Sn/Pb paste was deposited over the test boards through a stencil printing process, components were placed with a GSM and the assemblies were reflowed in a forced convection reflow oven.

The test board, surface mount devices, stencils, and build matrix were designed to address several outstanding issues which included:

1. Placement of 0.4mm pitch devices using a paste printing process.
2. High yield placement of 0.5mm pitch TQFN.
3. Assembly of “mixed” CSPs (Pb-free solder bump assembled with Sn/Pb solder paste).
4. Air-to-Air Thermal Cycle (AATC) Reliability of assembled devices. (To be presented in future reports).

The following report provides basic test board design, component construction, paste information and stencil details. All major assembly details including printer settings, pick and place operations and reflow profiles are also presented. Post-assembly inspection and analysis may also be found in this report.

Evaluation of Printed Circuit Boards Produced in China
Author: Thomas R. Homa
Abstract: This report describes the result of construction analysis of printed circuit boards produced by nine different Chinese vendors. A via chains section from eight vendors were placed in a 0-100C thermocycle chamber for 2000 cycles and the results are included in this report.

Immersion Ag Thickness Variations: A Brief Case Study
Authors: Shafi Saiyed, K. Srihari and Pericles Kondos
Abstract: Area array components assembled onto printed circuit boards with immersion silver finishes have shown a sometimes extremely large scatter in reliability. As part of an investigation into the possible causes for this, typical Ag layer thicknesses actually received from various suppliers were quantified. Great variability and large deviations from the thicknesses ordered, and those eventually reported by the suppliers, were common. The present document reports results for boards plated using the so-called Alpha Level chemistry, which is supposed to offer a truly self-limiting process and which does not appear to cause an unusual scatter in solder joint reliability. In fact, Ag thicknesses proved extremely sensitive to the feature size, exceeding the supposed limit by almost an order of magnitude on small pads, as well as varying with location and exhibiting a limited overall reproducibility. Sample calculations show that these variations can have a significant effect on the final composition (and hence presumably on the properties) of solder joints in very fine pitch assemblies.

Mixed No-Pb/Sn-Pb Assemblies: Their Microstructure and Its Evolution
Author: Pericles A. Kondos
Abstract: The microstructure of mixed lead-free and tin-lead assemblies was examined for many types of components, lead-free compositions, paste volumes, and reflow conditions. Special attention was given to the number, size, and location of the Ag3Sn platelets as they might possibly have an effect on the reliability. It was seen that when the maximum temperature remained below the melting range of the SAC alloy, partial reflow of the solder joint often took place, and the dissolution of pre-existing platelets could not be assured. In some components no platelets were seen after reflow. Areas with a eutectic-like structure, with the Ag3Sn appearing in the form of long, narrow, more-or-less parallel particles were seen. These particles ripened during thermal cycling. The cracks developed in the joint during cycling were examined, and instances where platelets could have helped the cracking of the joint were discovered.

Reliability of Reworked 0.4mm Pitch Wafer-Level Chip Scale Package Assemblies
Authors: Laurence A. Harvilchuck and Muffadal Mukadam
Abstract: This study details the reliability of reworked 0.4mm pitch assemblies. Lead-bearing (SnPb) and lead-free (LF-2) alloy bumped components were subjected to rework using standard protocols and then subjected to air-air thermal cycling (AATC) until failure. Results show that, in this case, the reliability of reworked LF-2/SAC (SnAgCu) assemblies is equivalent to the original assembly. SnPb components suffered a minor reduction in reliability attributable to reduced reflow temperatures. Situations unique to fine pitch components are discussed herein.

“Rework of SnPb, SAC, and Mixed Alloy Based 0.4mm Pitch Wafer-Level Chip Scale Assemblies”
Authors: Laurence A. Harvilchuck and Muffadal Mukadam
Abstract: This study details the rework of 0.4mm pitch assemblies with SnPb, SAC (SnAgCu), and mixed SAC/SnPb solder joints. Deviations from and exceptions to standard protocols are discussed, with special attention paid to issues regarding fine pitch components.

Rework of Underfilled 0.4mm Pitch Wafer-Level Chip Scale Assemblies
Authors: Laurence A. Harvilchuck and Muffadal Mukadam
Abstract: Capillary underfilling of fine-pitch wafer level chip-scale packages (WLCSPs) distributes the destructive stresses resulting from thermal fatigue and/or mechanical shock, usually at the cost of sacrificing reworkability. Several new materials offer to combine the durability of underfill with the prospect of future rework. Three materials showing promise for repair are evaluated here, with attention to those issues indigenous to fine-pitch assemblies.

Reliability of 0.4 mm Pitch WLCSP Assembled with Combinations of SnPb and SAC Solder
Authors: Muffadal Mukadam, K. Srihari and Peter Borgesen
0.4mm pitch WLCSPs were assembled onto printed circuit boards with mixtures of SnPb and SnAgCu solder. Effects of assembly parameters were quantified in 0-100oC thermal cycling. It was argued that reflow profiles need to be hotter for the assembly of components with SnAgCu balls and SnPb paste than for pure SnPb assembly. Effects of thermal cycling parameters were also briefly addressed.

Arguments were presented for assuming previously reported reliability data for pure SnPb assemblies to be too low.

Reliability of SAC Based 0.4 mm Pitch WLCSP Assemblies
Authors: Muffadal Mukadam, K. Srihari and P. Borgesen
Abstract: The present report documents the reliability of SAC solder joints connecting an 0.4mm pitch WLCSP to a typical 62 mil thick PCB. Reliability is here quantified as the fatigue life in 0-100oC thermal cycling, and it is found to be almost twice as high as for SnPb solder joints at the present dimensions and cycling conditions. A scaling with component size and solder joint volume is established by comparison with results for 0.5mm pitch WLCSPs and an 0.2mm pitch flip chip. The scaling does not account for, among other, dependencies on hold times and heating/cooling rates in cycling. The importance of the latter was roughly assessed by raising both heating and cooling rates by more than an order of magnitude.

“Alternate Lead Finish QFP Assembly and Lead Pull Study Includes Sn/Pb, Sn, Sn/Cu, & Ni/Pd/Au Lead Finish”
Authors: Muffadal Mukadam, Michael Meilunas and K. Srihari
Abstract: This report summarizes the lead pull test results for four unique quad flat pack (QFP) component lead finishes. The lead finishes evaluated were tin (Sn), tin-copper (Sn/Cu), nickel-palladium-gold (Ni/Pd/Au), and tin-lead (Sn/Pb). The QFPs were subjected to pre-assembly steam age conditioning and post-assembly temperature aging prior to the pull test.

Assembly was performed on UIC demo boards. Three 208-leaded .5mm pitch QFP components were assembled on each board. Two solder pastes were used for the assemblies: tin-silver-copper (Sn/Ag/Cu) and tin-lead (Sn/Pb).

The assemblies were characterized by visual inspection, X-ray inspection, and representative cross-sectional analysis prior to the pull test. Microscopic examination of the fracture surfaces was performed following the pull test. Solder void formation, non-wets, and failure mechanisms encountered during the experiment were documented for every QFP and the inspection results were correlated to the pull test data.

This report is a brief update to “QFP Assembly and Lead Pull Study” and provides the complete pull test results for the entire experiment including that of the Ni/Pd/Au finished QFPs and the results for 500 and 1000 hour temperature aging. Please refer to “QFP Assembly and Lead Pull Study” for additional process information, failure analysis, and representative images.

Overall, the results are encouraging. The pull test data indicates that the alternate surface finished QFPs produce solder joints that are as good as or better than the Sn/Pb finished QFPs. Defects were introduced by an 8 hour steam age conditioning, but the occurrence of the defects was similar to those observed with the Sn/Pb baseline. Long term temperature aging was shown to significantly decrease the strength of the alternate finished QFP solder joints, but once again, the difference was similar to the Sn/Pb baseline.

Ball Grid Array: Reballed & Reworked Reliability
Authors: Michael Meilunas and Arun Gowda
Abstract: Universal Instruments’ Consortium Test Board 8 side B (TB8-B) was designed to evaluate assembly and reliability issues associated with daisy-chained 1.27mm pitch, 256 I/O ball grid array (BGA) devices. Immersion tin TB8-Bs were assembled in early 2003 with BGA design “J3” using Sn/Pb paste or flux printing processes. Half of the board level assemblies were left “as is”, while the remaining half of the assemblies were reworked under different process conditions and then subjected to air-to-air thermal cycling to evaluate 2nd level reliability.

The following report describes the test board design and component construction while providing information concerning the assembly and rework processes important to the build. Post-assembly and/or rework inspection and analysis may also be found in this report.

The data indicates that reworking and/or reballing the BGA had little impact on the reliability of the assemblies. The rework and reballing processes evaluated did not appear to affect the failure mode or mechanism encountered in the various assemblies. Slight differences in reliability were observed, but the differences were most likely influenced by specific process parameters (such as paste versus flux assembly) than by the actual rework procedure.

Update on the Characterization and Reliability of Non-Molded Flip-Chip BGAs and CSPs
Author: Michael Meilunas
Abstract: A non-molded component is an electronic package whose die has not been coated with a mold compound, also called an overmold. Traditional BGAs and CSPs require overmolding in order to shield the active surface of the die from the environment and to provide mechanical support to the first level wirebond connections. However, flip-chip in package BGA and CSP designs encapsulate the active surface of the die and have no need for wirebonds. Non-molded flip-chip BGAs and CSPs are slimmer, lighter, and potentially cheaper than their molded counterparts and may be assembled to printed circuit boards using the same processes as traditional molded components.

The following paper describes the characterization and assembly of two non-molded components: a BGA and a CSP; and compares the thermal cycle and mechanical reliability of the packages to equivalent molded components. The reliability experiments included air-to-air thermal cycling, torsion (cyclic twisting), and drop testing.

The experiments show for the devices evaluated, that the 2nd level interconnections of the non-molded package assemblies are mechanically more robust and less susceptible to thermal cycle induced fatigue than their overmolded counterparts. The average reliability increase was between 20 and 35% for the three experimental conditions evaluated. The improvements were attributed to the reduced weight and increased flexibility (i.e., stiffness reduction) of the non-molded devices.

“CSP Reliability on .010″” and .012″” Flexible Printed Circuit Board #9″
Author: Michael Meilunas
Abstract: The following report describes the results of air-to-air thermal cycling performed on flexible substrate assemblies. The experiment was designed to evaluate the reliability of single and double sided CSP assemblies on 4-layer and 6-layer polyimide printed circuit boards (PCB).

Surface mount devices representing flexible CSPs, laminate CSPs and laminate LGAs (land grid array) were assembled single sided and in various double sided combinations on both the 4-layer and 6-layer flexible boards. The results of the thermal cycle test were analyzed and found to be highly dependent upon the device type, PCB layer count and assembly combination (single sided or double sided). In general, the 4-layer PCB design produced lower single sided reliability than did the 6-layer design, but both board designs produced similar double sided reliability results.

The single sided data was then compared to existing information obtained on non-flexible FR4 based PCBs for each device type. The comparison produced mixed results with some devices performing better on the flexible boards while others performed better on the FR4 boards.

This report contains a brief description of the test boards, surface mount devices, and parameters investigated. The results of the air-to-air thermal cycle test are presented and compared to results obtained on thicker, FR4 boards. Excerpts and figures found in this report have been taken from “Chip Scale Package Polyimide-Flex Test Board #9” which contains a thorough discussion on the test board and package designs, assembly process and the results of mechanical testing performed on the flexible boards. The results of this experiment are not clear-cut and further investigation using finite element modeling is underway.

“Reliability of Double Sided BGA and QFP Assemblies on Thin (.031″”) and Thick (.093″”) Printed Circuit Boards”
Authors: Michael Meilunas, Shiva Kalyan Mandepudi and K. Srihari
Abstract: This report describes a companion experiment to “Reliability of Double Sided BGA and QFP Assemblies” published by the Area Array Consortium 2002. The previous research established the reliability of mirror image BGA and BGA opposite QFP assemblies on .062” thick printed circuit boards (PCB) and compared the results to the single sided conditions. This research further advances the study by comparing similar single and double sided assembly combinations on thinner .031” PCBs and thicker .093” PCBs.

Past work has shown that the reliability of single sided assemblies improves when the board thickness is reduced. However, there are indications that the same does not hold true with double sided assemblies. Pitarresi et al have created finite element models (FEM) of double sided assemblies on .032”, .062”, and .093” PCBs. Their data suggests that the reliability of double sided PBGA assemblies actually decreases as the board thickness decreases (for the range of thickness’ evaluated). The models also showed that the reliability of double sided CSP assemblies was greatest when the devices were assembled to the .062” PCB –indicating that an optimum board thickness may exist for a particular assembly.

The current study was designed to investigate this phenomenon by assembling PBGA devices on .031” and .093” PCBs in mirror image double sided and single sided configurations and testing the assemblies in air-to-air thermal cycling (AATC). The reliability results, along with those published in “Reliability of Double Sided BGA and QFP Assemblies”, were then compared. The data indicates that the reliability of double sided assemblies is dramatically affected by the PCB thickness. The thermal cycle results showed that the reliability of a double sided assembly on the .031” PCBs was slightly better than that of similar assemblies on .093” PCBs, but both combinations were far superior to double sided assemblies on .062” PCBs.

This study also evaluated the effects of a compliant backside device on the reliability of PBGA packages. A QFP was assembled opposite the PBGA devices and the assemblies were tested in AATC. The results indicated that the QFP had little impact on the reliability of the opposite side BGA device for .031”, .062” and .093” PCBs.

“Effect of Printed Circuit Board Surface Finish on the Air to Air Thermal Cycle Reliability of Chip Scale Packages: ENIG, Copper OSP and MacDermid- ImmAg”
Author: Michael Meilunas
Abstract: This report intends to describe the assembly and test of several Pb-bearing chip scale package (CSP) designs on electroless nickel / immersion gold (ENIG), immersion silver (ImmAg), and copper OSP printed circuit boards (PCB). The main focus of the research was to determine if the air to air thermal cyclic reliability of the 2nd level CSP solder joints was significantly affected by PCB surface finish. Package types included flexible CSPs, micro leadframe CSPs, wafer level CSPs, laminate based CSPs, and a ceramic CSP.

Air to air thermal cycling with concurrent event detection was performed on the assemblies in order to compile failure data for each package type / printed circuit board combination. The cycle to failure data was analyzed using Weibull analysis and compared. Extensive failure analysis was also performed to identify the dominant failure mechanism(s).

The results indicate that the printed circuit board surface finish affected the reliability of many of the devices tested. In general, the ENIG assembled devices produced a substantially lower reliability (N63.2) than the copper OSP and immersion silver assembled devices. It was also observed that the immersion silver assembled devices failed gradually –often producing the earliest failures and the latest failures.

Effect of PCB Pad Geometry and Surface Finish on BGA Solder Joint Strength in Shear Testing
Author: Michael Meilunas
Abstract: BGA and CSP devices are typically reflow soldered to circular printed circuit board (PCB) pads. These pads may be solder mask defined (SMD) or non-solder mask defined (NSMD) and often contain via structures. These features directly affect both the solderable pad area and solder joint shape and therefore influence the mechanical robustness of the assembly.

Printed circuit boards are plated, or finished to maintain solderability. Immersion gold over electroless nickel (ENIG) and copper OSP (OSP) are widely utilized finishes. Immersion silver (Ag) has recently been adopted by NEMI as a suitable finish and is gaining popularity in the electronics industry. The surface finish determines what intermetallic phases form during reflow soldering and influences the mechanical properties of the bulk solder.

Shear testing was used to evaluate the mechanical strength of Sn/37Pb solder joints assembled to twelve PCB pad shapes representing SMD and NSMD designs with a variety of additional features. Each PCB pad design was tested with ENIG, OSP and Ag surface finishes. The results indicate that slight modifications to the traditional pad designs can statistically improve the mechanical robustness of the solder joints and that the surface finish is an important factor determining shear strength.

Mixed CSP Reliability ” Phase II An Analysis of Pb-Free Devices Assembled with Sn/37Pb Paste and Reflow Conditions
Author: Michael Meilunas
Abstract: This report discusses the air to air thermal cyclic reliability of Pb-free CSP devices assembled using Sn/Pb paste and reflow profiles developed for Sn/Pb assembly.

Sn/Ag, Sn/Ag/Cu, and Sn/Ag/Cu/Sb devices were placed on copper OSP finished circuit boards printed with Sn/Pb paste and reflowed using a standard ramp-soak-ramp style profile developed for Sn/Pb assembly (ie, a peak reflow temperature of 213 – 221oC). The devices were then subjected to air to air thermal cycling in order to stress the second level solder joints. Electrical continuity was monitored in-situ and cycle to failure data was recorded for each device.

Reliability data was computed using 2-parameter Weibull plots. The data for each mixed alloy combination was then compared to a pure Sn/Pb baseline. Failure analysis was performed and included cross-sectioning and metallographic/SEM examination.

This report describes the components and test board design, assembly procedures, test conditions and initial failure analysis. The primary goal of this research project was to determine the reliability effects of mixing Pb-free and Sn/Pb solder alloys using a Sn/Pb reflow profile and comparing the results to the “pure” Sn/Pb baseline.

The experiment found, that for the conditions evaluated, mixed alloys created with Pb-free solder bumps and Sn/Pb paste produced significantly less reliable solder joints than the pure Sn/Pb baseline. In fact, the first mixed alloy failures occurred 57 – 75% earlier than the first Sn/Pb failure.

Mixed CSP Reliability ” Phase III An Analysis of Mixed Alloy Solder Joints Created Using Sn/Pb and Pb-Free Reflow Profiles
Author: Michael Meilunas
Abstract: This paper documents the assembly and testing results of the mixed alloy CSP build on Universal Instruments’ Test Board 8 revision B side B. The mixed alloy build was designed to address assembly and reliability concerns associated with combining Sn/37Pb and Pb-free solder alloys using various “real-world” reflow processes.

CSP devices were obtained with Sn/37Pb and/or Pb-free solder spheres and were assembled to Omikron immersion tin plated printed circuit boards with Sn/37Pb and Sn/3.5Ag/0.7Cu solder pastes using standard Sn/37Pb reflow temperature profiles and Pb-free reflow temperature profiles. Post assembly inspection included electrical measurements and x-ray examination. Severe handling conditions were also simulated in order to stress the solder joints in selected assemblies.

The remaining assemblies were subjected to 0/100oC air to air thermal cycling in order to evaluate the fatigue resistance of the 2nd level mixed alloy solder joints. The cycle to failure data was compiled and analyzed using Weibull analysis and compared to “pure” Sn/37Pb and Pb-free assemblies. The results of the experiment were “mixed”. The data indicated that the reliability of the pure Pb-free system was superior to that of the other alloys evaluated and that the mixed alloys could perform significantly better, equal to, or significantly worse than the Sn/37Pb alloy. The extent of the reliability improvement or reduction was related to the package type and mixed alloy composition. An effect due to the reflow profile was observed, but was found to be a less significant factor.

Reliability and Failure Analysis of Flip-Chip CSPs and Flip-Chip LGAs
Author: Michael Meilunas
Abstract: This paper discusses the air to air thermal cycle reliability of flip-chip chip scale packages (fcCSPs) and flip-chip land grid array (fcLGA) devices. A brief overview of the packages, printed circuit board (PCB), assembly process and test methods are provided. Reliability estimates were computed using 2-parameter Weibull plots. Failure analysis included cross-sectioning, dye and pry, and SEM evaluations. In addition to CSP versus LGA, variables studied included PCB pad size and package attachment pad design variations.

The thermal cycle testing results show that the reliability of the fcLGA is similar to that of the fcCSPs. The results also show, for the conditions evaluated, that the reliability of the devices on .008” diameter PCB pads is better than the reliability of the devices on .009” PCB pads.

Reliability Analysis of Polymer Collar and Pb-Free Wafer Level CSPs
Author: Michael Meilunas
Abstract: This paper discusses the air to air thermal cycle reliability of LF2 (Sn/3.5Ag/1.0Cu) bumped wafer level CSP devices and Sn/Pb bumped polymer collar supported wafer level CSP devices. The results are compared to that of similar Sn/Pb bumped devices without polymer collars. The devices, printed circuit board (PCB), assembly process, and test methods are provided. Reliability estimates were computed using 2-parameter Weibull plots. Failure analysis included cross-sectioning, dye and pry, and metallographic examination.

The results of this experiment have shown that the addition of a polymer collar around the CSP solder joint near the device attachment pad can improve the reliability of the device without shifting the failure mechanism. For the device type evaluated, the addition of a polymer collar was shown to improve the reliability more so than transitioning from Sn/Pb to Pb-free assembly.

Reliability of Underfilled 0.4mm Pitch Wafer-Level Chip Scale Packages Before and After Rework
Authors: Laurence A. Harvilchuck and Muffadal Mukadam
Abstract: Underfilling fine-pitch wafer level chip-scale packages (WLCSPs) reduces the risk of damage in mechanical shock and may reduce thermal fatigue, often at the cost of sacrificing reworkability. Three underfill materials showing promise for repair were evaluated for the use with 0.4mm pitch components elsewhere: two capillary underfills and one used only for perimeter and corner reinforcement. The present report addresses first data on the resulting reliability of the latter.

Reliability of Double Sided Assemblies on Test Board J
Author: Michael Meilunas
Abstract: The 0/100oC air-to-air thermal cyclic reliability of several double sided assembly combinations were evaluated and compared to the single sided baseline. The assemblies included mirror image configurations and “mismatched” configurations. The mismatched configurations included flexible CSP opposite MLF, laminate CSP opposite flexible CSP, and laminate CSP opposite MLF.

The cycle to failure data was analyzed using Weibull plots. The results indicated that the reliability of most of the devices decreased when assembled opposite another package. However, the results showed that the reliability of the flexible package types could be improved over the single sided baseline if the opposite side device was a laminate CSP or MLF. No configurations were encountered in which the reliability of both back-to-back packages increased when compared to the single sided conditions.

Reliability Analysis of Mixed Alloy CSPs – Phase I: A Preliminary Study on the Combining of Pb-Free and Sn/Pb Alloys
Author: Michael Meilunas
Abstract: This paper discusses the air to air thermal cycle reliability of mixed CSP assemblies. Otherwise identical CSP devices were obtained with Pb-free and Sn/Pb solder bumps and assembled with Pb-free and Sn/Pb pastes. Both ENIG and Immersion Ag PCB surface finishes were used. Reliability estimates were computed using 2-parameter Weibull plots and compared to a Sn/Pb baseline. Failure analysis included cross-sectioning, dye and pry, and metallographic/SEM examination. The experiment was Universal Instruments’ first mixed reliability study and the results were used to direct future projects.

In addition to reliability data, basic component construction, test board design, assembly procedures and failure analysis have been documented in this report.

The test results clearly show that Pb-free devices assembled using similar Pb-free solder pastes produced the most reliable solder joints. However, the mixed alloy systems often produced “mixed” reliability results. That is, the combining of a Pb-free alloy with Sn/Pb could either improve or reduce the reliability of the new alloy when compared to the Sn/Pb baseline.

Reliability of Reworked Mixed Alloy 0.4mm Pitch Wafer-Level Chip Scale Assemblies
Authors: Laurence A. Harvilchuck and Muffadal Mukadam
Abstract: This study details the reliability of reworked mixed alloy 0.4mm pitch assemblies. Two paste and bump alloy combinations were subjected to rework using standard protocols and then subjected to air-air thermal cycling (AATC) until failure. Situations unique to mixed alloy assemblies are discussed herein, with special attention paid to fine pitch components.

Reliability of SnPb Based 0.4 mm Pitch WLCSP Assemblies
Authors: Muffadal Mukadam, K. Srihari and P. Borgesen
Abstract: The present report documents the reliability of SnPb solder joints connecting an 0.4mm pitch WLCSP (Package BU) to a typical 62 mil thick PCB. Reliability is here quantified as the fatigue life in 0-100oC thermal cycling. Optimization of the solder paste printing process did not appear to make a significant difference. Separate reports will address the reliability achievable without printing, and the reliability and repair of underfilled assemblies [8, 9, 10][/8,].

Thermal Cycle Reliability Analysis of the 2577 I/O Hyper BGA
Author: Michael Meilunas
Abstract: This report describes the Air-to-Air thermal cycle testing results of the 1.0mm pitch, 2577 I/O HyperBGA devices. Variables evaluated included PCB pad diameter and original assembly versus rework assembly. The reliability data has been evaluated using a Weibull distribution and standard failure analysis procedures were followed to determine the failure mechanisms encountered.

This report also contains a brief description of the test board and HyperBGA construction and provides references to the assembly and rework procedure documentation.

The experiment has determined that the thermal cyclic reliability of the device is sufficient for its intended applications. The reliability of the device was improved by assembling to larger PCB pads but was decreased by flux-only rework.

Mixed Hybrid Assemblies: NanoSphere Wafer Scale Package
Author: Thomas R. Homa
Abstract: This study will evaluate the assembly window for the Texas Instruments NanoSphere wafer scale package with lead-tin and two different lead free solder bump alloys. All bump alloys were assembled to test boards with both eutectic and lead free solder paste. The component fatigue life was evaluated over a variety of reflow temperatures, solder paste volumes, board finishes, and accelerated test conditions. These assembly parameters were evaluated with a full factorial experiment to determine how assembly parameters would affect fatigue life. The work will proceed in two stages. In the first stage, assemblies with 224 different combinations of parameters will be cycled in torque to identify parameters with a particularly strong negative effect on joint properties. Aside from the direct relevance of this information to mechanical robustness concerns, this information can be used to design the thermal cycle portion of the study. With the information gained from the fatigue study, we can reduce the number of variables and increase sample size to improve the statistical significance of accelerated thermal cycling (ATC) results.

Codification Software 2003 Updates
Author: Antonio Prats
Abstract: The ‘Codification Software’ is a decision support / expert system, which serves as a guide (knowledge base) for process and design engineers in the electronics manufacturing industry. It was developed and is maintained by the Area Array Consortium at Universal Instruments. This year the updates include addition of new components to the component database and the additions of more reliability testing.

Area Array Consortium 2003 Overview
Author: Peter Borgesen
Abstract: In 2004 a major emphasis of our Area Array Consortium sponsored efforts will be on the development of process manuals, or ‘cook-books’, guidelines, tools and practical recommendations. Many of the underlying issues have been researched in considerable depth over the years, and most of our 2003 efforts were aimed at ‘filling in the gaps’. Some of the efforts were relatively new, including those on thermal interfaces, stud bumped flip chips, immersion Ag pad finishes, and mixing of no-Pb and SnPb solders. The latter in particular had been initiated earlier, but the urgency of the issue became evident a year ago and our efforts were scaled up accordingly.

The present document and an accompanying overview of flip chip issues review our 2003 work with references to the individual progress reports and selected presentations included on the 2003 CD. It is recommended that readers start here to ensure the proper perspective and to check for the most recent updates to our learning. This is particularly important in the area of mixed solders where initial process recommendations are attempted.