1998 Reports

Downloads & Resources

Chip Scale Package Program: Complete Summary
Author: Anthony A. Primavera
Abstract: Current standard surface mount devices such as peripheral leaded packages and area array devices offer robust assembly yields and good long term solder joint reliability. New devices and packaging methods must compare to or perform better than standard devices in assembly and reliability arenas in order to gain acceptance and wide use. In an attempt to achieve the functionality and density of bare die assembly, a new family of devices has been developed by the packaging industry which are very close to the dimensions of the bare silicon die. Chip Scale Packages (CSP) are defined as devices only slightly larger than the die. These devices satisfy the demands of miniaturization while retaining the advantages of conventional packages. CSPs have been assembled using conventional surface mount techniques and the long-term solder joint reliability has been assessed for over 2 dozen different components. This report is a final overview and summary of the CSP half of the Consortium. A complete process, materials and reliability summary is presented. Further information about each topic is available in supporting documents and reports, which are referenced in this report.

Package Introduction And Overview
Authors: Anthony A. Primavera and Suresh Jayaraman
Abstract: Continuing growth in complexity levels of silicon integration and circuit functionality have spurred a growth in interconnection densities in packaging technology. Increased complexity has gained a considerable reduction in board real estate while simultaneously providing a solution for more chip functionality and larger Input and output capacity. The ultimate package would be capable of performing all functions on the single integrated circuit. The trend of current processor design certainly shows the trend in this direction. Assembly of the bare integrated circuit onto a mother board, eliminates the first level of package technology and consumes the least board real estate of current surface mount devices. The two methods used to attach the die to the mother board are chip on board, utilizing wirebond technology, and flip chip assembly. In both methods, assembly processes have to overcome challenges such as bare die handling, individual die processing steps such as wirebonding and encapsulation, underfill dispensing, as well as testing and providing a fully functional known good die.

Current standard surface mount devices such as peripheral leaded packages and area array devices offer robust assembly yields and good long term solder joint reliability. New devices and packaging methods must compare to or perform better than standard devices in assembly and reliability arenas in order to gain acceptance and wide use. In an attempt to achieve the functionality and density of bare die assembly, a new family of devices has been developed by the packaging industry which are very close to the dimensions of the bare silicon die. Chip Scale Packages (CSP) are defined as devices only slightly larger than the die. These devices satisfy the demands of miniaturization while retaining the advantages of conventional packages. CSPs have been assembled using conventional surface mount techniques, but have been plagued with long term reliability problems. This report reviews various CSPs that are under development and in production and introduces issues associated with long term reliability.

Process Overview – Rework Of Chip Scale Packages
Authors: Parvez M.S. Patel and K. Srihari
Abstract: The focus of this research was devoted to understanding the rework process for the Chip Scale Packages (CSPs). A robust rework process was developed at the Universal Instruments Corporation, Surface Mount Technology Laboratory. The main goal of the study was on the characterization of the rework system and the heating criteria’s adopted, developing robust component removal, site redressing, and component replacement process. In addition, the different solder replenishment methods were studied and compared. The goal of any rework operation is to create assemblies that have reliability as good as, if not better, than non-reworked assemblies.

The following report explains the process issues and concerns involved in the rework of CSPs and Surface Mount Assemblies. The various factors affecting the reliability and the yield of the reworked components are discussed. This report provides a summary of the results obtained from the CSP rework related experiments that were performed within the CSP/DCA Consortium. Process consideration and recommendations for each step of the CSP rework process are presented.

Moisture Absorption/Desorption Study For Chip Scale Packages
Authors: Ashish Alawani and K. Srihari
Abstract: As semiconductor devices continue to be designed into smaller, lighter and thinner packages, the inherent moisture sensitivity of the materials used to fabricate plastic packages tends to become a serious issue. Whereas, components do need to be moisture free for the initial assembly process (where sufficient control can be achieved by effective handling of the component), any presence of moisture may prove to be extremely critical when the components are returned for rework or are to be removed for reuse or failure analysis. Chip Scale Packages (CSP) are the latest in the succession of plastic semiconductor devices that tend to exhibit susceptibility to moisture-induced package cracking.

In order to investigate this effect in CSPs, moisture absorption trends were studied for 14 different types of packages. Effects of multiple absorption and desorption cycles on the moisture sensitivity of the packages were studied. A desorption study was conducted to determine adequate and practical bake out times for these components. A delamination study, using JEDEC (level III) specified test, was conducted to obtain the theoretical, critical moisture content that would lead to delamination of the packages.

Of all the packages studied, package “C” showed the maximum average percentage moisture gain. The moisture desorption study showed that a bake out time of 4 – 5 hours is sufficient to prevent the delamination of packages during reflow. The package “L” was also included in the JEDEC level III testing of the packages. Micro CSPs “O” and “P” were not included in the delamination study as they did not show any sensitivity towards moisture and exhibited negligible weight gain. Nine components were included in the delamination study and all the packages, including the package “L”, passed the third level JEDEC test and did not show any failure due to popcorning. Cross-sectional analysis of package “C” also did not show any noticeable delamination. To ascertain the behavior of the 3 laminate packages (“D”, “E” and “F”) and 2 flex packages (“A” and “B”) in a moisture-induced environment, the packages were subjected to the JEDEC level I test (85C / 85%relative humidity). The flex packages successfully passed the test, while all the laminate packages showed a fair degree of delamination.

Characterization Of Tessera Tv 46 Micro Bgas
Authors: Anthony Primavera, Krishna Kalyan, Sanjay Sharma and K. Srihari
Abstract: Micro BGA packages from Tessera Corporation were studied with respect to the variation in the solder ball volume, the moisture absorption/desorption characteristics, moisture level classification, and warpage at room temperature as well as at reflow temperature. Assembly yields were predicted based on the observed and hypothetical variations using a Monte Carlo based simulation technique. While the warpage did not significantly affect the assembly yields, variations in the contact pad sizes and solder volume had a significant impact on the assembly yields. Board pad recommendations based on the results from simulation studies are provided.

Overview Of Csp Warpage Issues
Authors: Robert Fenton and James M. Pitarresi
Abstract: The study and understanding of thermally induced deformations in chip scale packages (CSP) is important to the development of this technology. The understanding of warpage is important for the characterization of electronic components. The thermal loading of the component is a major concern during the reflow assembly process. If warpage is excessive, the solder joint will bridge or gap, creating the need for component repair or replacement. Also, the shape of the solder joint will change due to this deformation causing concerns with the component’s reliability. Through control of the warpage phenomenon, the performance of a component may be optimized. The method of warpage characterization and the associated measurement techniques are discussed.

Shadow-Moire Interferometry Of Selected Electronic Packages For The Universal Instruments Consortium
Authors: Jonathan Rayner and James M. Pitarresi
Abstract: In this measurement, several chip scale packages were examined for room temperature warpage. The technique used in this examination was Shadow-Moiré interferometry. The results of this experiment led to several conclusions:

  • In several package types, the die and substrate side warpage are within +/- 1 mil of each other.
  • In most cases examined to date, the reflow temperature warpage does not change from room temperature more than 2 mils.
  • While warpage is an important consideration in electronic packages, careful attention should also be paid to other factors, such as package size, ball area array, and local warpage effects.

In-Plane Displacement Of Selected Chip Scale Packages And Printed Circuit Boards Using Moire Interferometry

Authors: Jonathan Rayner, Robert H. Fenton and James M. Pitarresi
Abstract: In this report, several Chip Scale Packages (CSPs) and some Printed Circuit Boards (PCBs) were examined using the Moiré interferometry technique. These measurements examine the in-plane displacement of the samples and allow us to examine the effective coefficient of thermal expansion (CTE). From these measurements, it was concluded that:

  • Using Finite Element Modeling, the measured values were compared to the theoretical predictions for effective CTE. The results of this experiment, coordinated with the results from the fatigue life predictions show some preliminary trends that, with more data, could be quantified.
  • It is seen that the models are able to predict the effective CTE of the components

Technical Report On Moire Interferometry
Authors: Jonathan Rayner and James M. Pitarresi
Abstract: In this experiment, our laboratory examined the capability of the Moiré interferometry technique in use with chip scale packages. This technique provides in-plane displacement measurements. From this data, the effective CTE and strains can be extracted. In this study, the following was learned.

  • Moiré interferometry is currently capable of measuring the in-plane displacements that occur between room temperature and an elevated temperature of several chip scale packages.
  • The effective CTE of the composite structure can be extracted.
  • More work needs to be invested to improve the accuracy of results for effective CTE.
  • The technique employed would prove ineffective in examining the strains in the solder joints in chip scale packages due to the small pitch of the soldier joints.

Brief Summary Of Chip Scale & Ballgrid Array Packages Under Evaluation In Csp/Dca Consortium
Author: Sanjay Sharma

Component Characterization Report
Authors: Anthony Primavera and Sanjay Sharma
Abstract: Under the CSP/DCA consortium many different packages were evaluated for issues such as construction methods, material properties, manufacturing defects, metrology and package reliability. These several samples represent a wide range of package both in the CSP and BGA type. Some of the important features of the samples evaluated include a pitch size, array type, construction and ball size. The samples had bump pitch between 0.5mm to 1.27 mm in an area, perimeter and depopulated array, number of I/O’s varying from 6 to 412 and package sizes of approximately 100 mil to 1000 mils with an overall package thickness of 28 mils to 70 mils. The packages have bump height varying from 7 mils to 24 mils and the bump diameter of 12 mils to 30 mils. The carrier material of the packages include flex, rigid, flex with elastomer, and Micro SMT’s. Sample package types varied from live, daisy chain and mechanical samples

This report consists of a description of the package construction details as observed from the package cross section, the statistical variation observed on the bump diameter, height, pad size, bump location and pitch. Also included are the results of the warpage study done at both the room temperature and elevated temperature. Results are also presented for the component level reliability study, such as Moisture sensitivity, exposure to high temperature and high temperature aging test. Details on the individual packages are given in the Appendices.

A Cost Comparison Of Csp With Alternate Packaging Technologies
Authors: Vinu Yamunan and K. Srihari
Abstract: Chip Scale Packaging has generated widespread interest in the electronics industry by virtue of the advantages it offers over existing technologies. Real estate savings, increased I/O density and superior electrical performance over the peripheral leaded devices are some of its qualities. Reliability, possible reworkability and robustness provide it an edge over Direct Chip Attach components. However, this is a relatively young technology and is therefore expensive. Other technologies like DCA can also be quite expensive because of the need for infrastructure, underfilling, slower throughput, and KGD issues, Etc.

The objective of this research is to develop a methodology that would assist a decision-maker with the economic justification for the use of CSP components in applications and products. The research methodology involves the comparison of the cost of assembling a board with one technology (such as QFP, BGA or DCA) with the cost of assembling a functionally equivalent board having CSPs. The values of the different cost facets are completely user defined. However, default values are also provided. The software model allows the user to save a set of input values from a run and reuse them, perhaps to perform sensitivity analyses on different facets of the cost. The metric used for the comparison is the assembly cost per board. The cost model has been developed using Microsoft Excel (Version 4.0).

A Preliminary Study Of Encapsulant Flow Behavior For Chip Scale Packaging Applications
Authors: Suresh Jayaraman and K. Srihari
Abstract: The capillary flow characteristics of three encapsulants were studied for standoff heights between 11-40 mils. The standoffs considered are typical of chip scale packages. The study was conducted to investigate the feasibility of encapsulation, using capillary flow, of CSP assemblies on printed circuit boards. Capillary action, which is the driving factor for encapsulant flow at low standoffs (1-5 mils), was studied for the higher standoffs.

Simple flow experiments were conducted to study capillary flow between glass slides. The variation of flow rates was measured as a function of standoff and surface morphology for three encapsulants (identified as Encapsulant 1, 2 and 3 respectively). The flow of Encapsulant 1 between a smooth glass slide on top and a frosted glass slide at the bottom, (and vice versa) was investigated to study the effect of the orientation of surface morphology on encapsulant flow. The effect of temperature on encapsulant flow behavior was studied for Encapsulant 3. The flow experiments that were conducted suggested that the three encapsulants studied had vastly different flow rates. Also, the sensitivity of flow rate to surface morphology seemed to increase with standoff for all encapsulant materials. The results of the study indicate that capillary action for encapsulant flow is still effective for a standoff height of 40 mils and is in fact stronger than the capillary action at lower standoff heights (1-5 mils).

Cu/Ni/Au Metallurgy Embrittlement Summary
Authors: Anthony Primavera and Robert Erich
Abstract: High temperature embrittlement and delamination of solder joints with attachment pad metallurgy utilizing Au and Ni plating over Cu pads. Several speculations as to the cause have been proposed as well as the questioning of some fundamental issues regarding Au over Ni plated systems. Supporting data and evidence for and against each speculation will be summarized.

Degradation Of Bga Solder Balls At Elevated Temperatures
Authors: Robert Erich and Peter Borgesen
Abstract: It has been observed that as some BGA devices are subjected to elevated temperatures for extended periods of time, the solder joints transform from a ductile state to a brittle state. This seems to be the case for BGA packages using the nickel/gold metallurgical system. The root cause for this problem is still unknown. This paper addresses the problem of solder joint embrittlement. An attempt is made to hypothesize what is actually happening as well as suggesting ways to study the phenomena and possibly determine, experimentally, what the cause is.

Investigation Of The Nickel/Gold Metallurgical System For Ball Grid Array Applications
Author: Robert Erich
Abstract: Brittle Failure has been observed on BGA components that use nickel/gold pad finishes over copper pads. This experiment studies several different nickel/gold metallurgical systems, as well as organic pad finishes and nickel/palladium. The goal of the investigation was to create solder joints using these various pad finishes, in both mask defined as well as pad defined geometry, and determine which, if any, show signs of brittle failure during shear testing. Shear testing was performed after ball attach as well as at several time intervals of isothermal storage at 150C. From the shear testing results, efforts were made to eliminate some of the possible causes for the embrittlement of BGA solder joints. The results indicated that brittle failure was generated on electrolytic nickel/gold and electroless nickel/immersion palladium samples. The brittle electrolytic samples were found to have excessive gold thickness from plating and gold embrittlement was blamed for the brittle failure. The reason for the palladium embrittlement has not been determined. Pad defined geometry yielded higher average maximum shear force during shear testing. Also, there were failures in the pad defined joints due to pad peel after significant thermal storage. The electroless nickel/immersion gold samples as well as all of the organic samples displayed ductile shearing throughout the testing.

Effect Of Shear Rate On Mechanical Strength Of Bga Solder Joints
Authors: Robert Erich and K. Srihari
Abstract: Experimentation has revealed that as some BGA components are subjected to elevated storage temperatures, the solder joints transform from a ductile to a brittle state. In an effort to study this phenomena, BGA ball shear testing was performed. It was found that shear testing is a good way to reproduce the solder joint embrittlement failure mechanism and expose the embrittled region for further examination. The experiment was done using a constant shear rate of 20 mils per minute. It may be the case, however, that the results obtained are a function of the shear rate. This investigation is designed to study effect of the solder ball shear rate on the maximum force, maximum displacement, and mechanical energy encountered in the ball shear process. Three different shear rates will be used: 1.8, 20 and 40 mils per minute. Each shear rate was used to shear off solder balls at 0, 20, 40, 60, 80 and 100 hours of high temperature storage at 150C. A Design of Experiments (DOE) approach is taken to determine the effect of the shear rate for maximum shear force, maximum displacement and mechanical energy. The results indicate that, for a 95% confidence interval, only the maximum force is statistically influenced by the shear rate. The results for the maximum displacement lay just beyond the region of statistical significance defined by the hypothesis test (at a 95% confidence interval). Duncan analysis revealed that the shear rates of 20 and 40 mils are not statistically different in any of the tests. It should be noted, however, that regardless of statistical significance, different shear rates can lead to different failure mechanisms in ball shear testing.

Shear Strength Testing Of Bga Components
Authors: Robert Erich and K. Srihari
Abstract: As Surface Mount Technology (SMT) continues to replace the traditional Through Hole Mount Technology (THMT), Ball Grid Array (BGA) technology has seen tremendous growth and success. While BGAs have gained in popularity due to high assembly yields, BGAs have exhibited lower robustness compared to standard SMT and through hole technology. It has been observed that as some BGA packages age, their solder joints transform from a ductile to a brittle state. This weakened interface may no longer be able to withstand the shear and warpage applied to it by thermal or mechanical loads. This is found to be a highly temperature sensitive phenomena. In this experiment, three different BGA packages (LSI 225 Daisy Chain, Motorola 225 OMPAC, and Amkor/Anam 204 SBGA) were subjected to accelerated aging at three different temperatures to determine the time-temperature relationship of embrittlement for each package. For each test component, the time to failure (joints become brittle) will be observed and recorded. It is expected that this degradation process will obey an Arrhenius rate function. From the graphical representation of the experimental data, the activation energy of the solder will be calculated which will make it possible to estimate the time to failure for any given temperature for each of the three packages. Conclusions drawn from this investigation are as follows:

1) High maximum shear force does not necessarily mean solder joints are good.
2) Strain and Joint displacement during shear are good indicators of the condition of the solder joint.
3) The time-temperature dependency for brittle failure does follow the behavior of an Arrhenius rate function.
4) The differences in package construction seemed to not play a role in the onset of brittle failure; it seems to be independent of package manufacturer.
5) For high temperature applications, handling and vibration prone applications, brittle failure could be a concern.

Direct Chip Attach Test Vehicle Design 1
Author: Anthony Primavera
Abstract: In an effort to focus on assembly of flip chip die onto low cost substrates, the first DCA Consortium test vehicle was designed and fabricated using conventional printed circuit board technology. Test vehicle 1, die were obtained from commercial vendors, Consortium Principal participation, and were fabricated by UIC staff in conjunction with the National Nano-Fabrication Facility at Cornell University. Die include perimeter array, staggered perimeter array, and non-uniform designs. Designs for the first test board included 1/4″, 1/2″, and 3/4″ die. Test chips for this board are the 8 mil pitch Delco die and a UIC designed 6 mil pitch staggered perimeter array. Test chip are a simple daisy chain stitched patterns to assess assembly parameters and board level reliability. Functional die applications included automotive, telephony, and consumer products will be assessed on other test board configurations. Several fully functional applications are being assembled and tested as part of the Consortium interaction with the Principal members. This document is a summary of test vehicle design 1 to be utilized in the project.

Chip Scale Package Brittle Failure Analysis
Author: Robert Erich
Abstract: Chip Scale Packaging (CSP) of integrated electronic circuits continues to grow in popularity in industry. Many CSPs are very similar in structure to commonly used packages such as Ball Grid Array (BGA) and Direct Chip Attach (CDA) packages. For this reason, some of the reliability concerns of these packaging styles are passed on to CSP technology. It has been observed that as some BGA packages are subjected to elevated temperatures for prolonged periods of time, the solder joint interconnections transform from a ductile state to a brittle state and, as a result, the weakened interface may no longer be able to withstand the shear and tensile forces applied to it by thermal and mechanical loading. In this report, an investigation of the 160 I/O, 1.0 mm. area array (CSP) is conducted to see if the phenomena of brittle failure occurs. Brittle failure has been observed in BGA components with the similar material properties. Shear testing was used as the test method used to determine the characteristics of the solder joint. The results show that brittle failure does occur. A failure prediction was made assuming that the degradation process can be modeled by using an Arrhenius rate function. From this function, the activation energy for the embrittlement process was calculated to be 30.1 kcal/mol with a material constant of 1.49 x 10-14. This predicts approximate failure times of 55 hours at 150C and 504 hours at 125C.

“””Double Side Assembly””-“”Rockwell Automation Build 1″””
Author: Anthony Primavera
Abstract: Assembly of chip scale packages (CSP) are becoming more common for memory and control applications. Investigation of the robustness of CSP assembly onto organic printed circuit boards (PCB) has been investigated in a laboratory setting at Universal Instruments Corporation as part of the CSP Consortium. While laboratory experimentation and design of experiments is extremely useful for process development, ultimately CSP assembly needs to be robust in manufacturing environments. Rockwell Automation has participated in evaluation of CSP assembly in conjunction with the Consortium in an effort design to understand the manufacturability of CSP products in a high volume assembly environment. Initial experiments were performed in the SMT Laboratory of Universal to establish a baseline process for the parts. Component and board evaluations were performed to characterize the mechanical and thermal properties of the materials used in the assembly. CSP Consortium build number 17 was performed to identify an initial process window for assemblies to be performed at Rockwell Automation. Assembly of 16 test boards during build 17 was accomplished with 100% joint yield. Double side processing of the panels resulted in no open joints after the second reflow pass and a subsequent third reflow pass showed no problems. The baseline process established during build 17 was a solder paste print using a DEK 288, pick and place using a Universal GSM1 and forced convection reflow using a Heller 1800 oven. A second base line build, build # 20 was performed on identical boards as the ones used at Rockwell. Report CSP Assembly Report Build # 20, details the assembly of components used on Rockwell test vehicles. The Rockwell Automation test plan included both double side reflow and single side reflow with a solder wave pass, see CSP Assembly Report Build # 23. The 112 panels assembled at Rockwell were broken down into 64 double side reflow and 48 wave pass.

Assembly of components onto CSPTB2 was accomplished in Build # 17 with 100 percent of the joints being formed properly. Electrical, X-ray, cross section analysis and visual inspection confirm proper joint formation and no defective joints. Double side assembly was successful with no components being disturbed during bottom side reflow. Samples of one package type were discovered to have become open after several weeks of room temperature storage. Two solder joints became open by a separation of the component ball from the component substrate. Evaluation of the samples showed properly formed fillets during assembly onto the test boards. The failures occurred at the nickel to solder interface at the component side of the joint. Accelerated thermal cycle testing of the packages are in progress at this time.

Csp Assembly Report Build # 23 – Rockwell Automation
Author: Anthony Primavera
Abstract: Assembly of chip scale packages (CSP) are becoming more common for memory and control applications. Investigation of the robustness of CSP assembly onto organic printed circuit boards (PCB) has been investigated in a laboratory setting at Universal Instruments Corporation as part of the CSP Consortium. While laboratory experimentation and design of experiments is extremely useful for process development, ultimately CSP assembly needs to be robust in manufacturing environments. Rockwell Automation has participated in evaluation of CSP assembly in conjunction with the Consortium in an effort design to understand the manufacturability of CSP products in a high volume assembly environment. Initial experiments were performed in the SMT Laboratory of Universal to establish a baseline process for the parts. Component and board evaluations were performed to characterize the mechanical and thermal properties of the materials used in the assembly. CSP Consortium builds number 17 and 21 were performed to identify an initial process window for the builds performed at Rockwell. Assembly of 16 test boards during build 17 was accomplished with 100% joint yield, despite component related problems. See CSP Assembly Report Build 17 for more information. The baseline process established during builds 17 and 21 was solder paste print using a DEK 288, pick and place using a Universal GSM1 and forced convection reflow using a Heller 1800 oven. The Rockwell Automation test plan included both double side reflow and single side reflow with a solder wave pass. The 124 panels assembled at Rockwell were broken down into 12 set up single side reflow boards, 64 double side reflow and 48 wave pass boards. Several problems were identified during the Rockwell build which are detailed in this report. Issues include paste slump, bridging of slumped paste, voiding, and a single bridged assembly after wave pass.

Chip Scale Package Build 24 (Micro Systems Engineering Customer Build)
Author: Mark S. Seus
Abstract: The purpose of this build was to examine the effects of building on a thin, unbalanced substrate. The end use of these assemblies requires them to be folded, hence the unique design. The analyses performed on these assemblies confirmed expectations of substantial board warpage. To minimize the affects of board warpage, full palletized assembly was performed. This led to successful assembly of the components. Implementation of thin, unbalanced boards in production environments requires the use of carriers to restrain the substrates.

Csp Assembly Report Build # 25 – Manufacturers Services Limited
Author: Anthony Primavera
Abstract: Assembly of chip scale packages (CSP) are becoming more common for memory and control applications. Investigation of the robustness of CSP assembly onto organic printed circuit boards (PCB) has been investigated in a laboratory setting at Universal Instruments Corporation as part of the CSP Consortium. While laboratory experimentation and design of experiments is extremely useful for process development, ultimately CSP assembly needs to be robust in manufacturing environments. Manufacturers Services Limited has participated in evaluation of CSP assembly in conjunction with the Consortium in an effort design to understand the manufacturability of CSP products in a high volume contract assembly environment. Initial experiments were performed in the SMT Laboratory of Universal to establish a baseline process for the parts. Component and board evaluations were performed to characterize the mechanical and thermal properties of the materials used in the assembly. The process at MSL was solder paste print using an MPM 3000, pick and place using a Fuji IPIII, and forced convection reflow using a Heller 1800 oven. The MSL test plan included single side reflow of panels in a 2 up format, using 3 pastes, 2 board pad finishes and 2 reflow atmospheres. Assembly included 2 BGA and 5 CSP types of components. 25 panels were fabricated, 1 set up board and 24 experimental boards. The 25 panels assembled at MSL were broken down into 6 lots of 4. Each group of 4 used a specific solder paste (3 sets of paste). Each lot of 4 contained 2 OSP and 2 Ni/Au boards. Of the 24 panels, half were reflown in open air and half were reflown in nitrogen environments. Of the 25 panels, 3 panels had 1 defective component. All components were the same type of device, but did not share paste type, board finish or atmosphere as a common variable. The lack of data clustered around a single cell, and the fact that the X-ray inspection showed no abnormalities, suggests defective components. Destructive analysis of the failed samples showed properly formed solder joints, thus indicating component related issues. Other process related issues included pick and place vision, and pick and place tray feeders.

Characterization Of High Density Test Boards
Authors: Suresh Jayaraman and K. Srihari
Abstract: The continuing trends of further miniaturization and portability of electronic devices have fueled a migration to new packages such as fine pitch Ball Grid Array (BGA), Flip Chip on Board (FCOB) and most recently Chip Scale Packages (CSPs). The advantages offered by these packages can be realized only if Printed Circuit Board (PCB) technology evolves to accommodate the fan out requirements of these packages. With the tightening of bump spacing and since most of the board area is now occupied by the bump land pattern array, the signal line width and spacing have to be drastically reduced in order to fan out the package Input/Outputs. Moreover, due to diminished real estate availability, the signal routing needs to be transferred to other layers in the PCB. This is achieved by incorporating miniature blind and buried vias (or microvias) which have currently challenged the development of compatible board fabrication technologies to support tight line widths/spaces.

The high density test boards were developed to evaluate the novel high density PCB options as they evolve and to help select the most appropriate technology for a given application. More importantly, it provides a common platform that allows the data generated at various places to be compared to an existing database (Tessier, T.G., et al., 1995). The high density test board is a generic test vehicle that was designed to be compatible with the major classes of existing high density PCB technologies based on photodefined, laser drilled, and plasma etched via generation. This enables the evaluation and the direct comparison of these via generation technologies for the reliability of the microvia interconnect structures, the accuracy and repeatability of the via dimensions, plating thickness and signal line widths/spaces.

This report provides the results of the measurements of flip chip pad diameters, via diameters, conductor widths and spaces and the via resistance measurements on the various high density test vehicles. A View Voyager 2000, an Automated Optical Inspection (AOI) equipment was used for the pad and hole feature size measurements. The measured feature dimensions are then compared to the original design dimensions, revealing some of the capabilities that a given high density board build-up technology has with respect to the minimum via diameter achievable, minimum conductor pitches and accuracy of these dimensions. The resistance of the via chains were measured using a HP multimeter. Also included are photographs of micro sections of vias in the three vehicles to understand the internal structures of the vias, such as the wall inclination angle, metallization thickness, and the top and bottom diameters. The results of the warpage measurement for the three boards, at room temperature, are also furnished. A Cyberoptics laser profilometer was used for the warpage measurements.

Csptb3 Pilot Build
Author: Mark S. Seus
Abstract: The results of builds 26, 27 & 28 were consolidated into a single group referred to as the CSPTB3 Pilot Build. The purpose for the pilot build was to develop an effective process for the new board. Additionally, the assemblies would provide a baseline for the characterization of CSPTB3 builds, as well as the reliability testing of them. The B and D sides of the board were populated on boards 0.031″ & 0.062″ thick. Metallurgy’s of Ni / Au and Cu / OSP were used with a variety of CSP’s.

In total, sixteen boards were built with four component failures being identified. Two of the failures could not be explained although no defects in the component joints were found. A device or PCB wiring fault may have been the reason for those failures. One failure was identified as being caused by a missing solder bump. The fourth failure was caused by warpage of the assembly and PCB sagging during the manufacturing process. It resulted in a height variation of approximately 15 mils across the length of the component (1060 mils) which led to the recommendation that any production build using thin boards should assemble them in a restrained fashion.

Reliability And Failure Analysis Of Chip Scale Packages
Author: Arun Rajagopalan
Abstract: The need for superior performance and economy of size, particularly in consumer electronics applications has driven the electronics industry towards smaller, more compact SMT packages. One of the technologies that have emerged from this need is Chip Scale Packaging. CSPs are Ball Grid Array packages with a package dimension/die dimension ratio of less than 1.2. The reliability of CSPs is of great interest to the packaging industry. The CSP/DCA Consortium at Universal Instruments has an ongoing Reliability Program to address this issue. A wide range of CSPs was obtained from consortium members, assembled on test vehicles under different parameters and subsequently underwent second-level reliability tests at different locations. This reports describes the second-level reliability experiments being conducted and the results obtained to date. Various parameters like PCB pad sizes and PCB metallurgies, PCB thickness are being investigated for their effect on reliability. The primary mode of failure was fatigue, driven by the CTE mismatch between the Si die and the PCB substrate. Instances of failures due to poor wetting, delamination, Ni/Au embrittlement, and voiding were also observed. The reliability program is scheduled to continue into the next year and will involve further testing and investigations of issues identified so far.

Machine Characterization – Rework Of Chip Scale Packages
Authors: Ashish Alawani, Parvez M. S. Patel and K. Srihari
Abstract: Several requirements need to be met when localized heating is used in an area array rework process. These requirements are independent to the nature of the rework station used, and are essential to establish a proper, standard rework process. This study aims at developing and establishing a certain set of parameters that would be applicable to the Chip Scale Package (CSP) rework process, independent of the type of assembly or the rework system used. It also evaluates the efficiency of the rework system in operating under the constraints set by the requirements of the CSP rework process. Three different profiles, based on three different heating strategies, were developed and evaluated with respect to their impact on the assembly and the rework process in general. Three different nozzles provided along with the rework system were studied. Suggestions were made to achieve repeatable profiles and to improve the heating scheme. A warpage study was conducted on 16 mil and 62 mil thick boards using the three profiles.

Based on the evaluation of the three profiles with respect to a specific criteria, it was found that the profiles are only marginally different in their performance. Hence, it is recommended that profile 3 be used for further experiments on component removal and replacement processes, since it (the profile) is much easier to generate and control using the software setup on the system.

Finite Element Modeling Of Chip Scale Packages
Author: James M. Pitarresi
Abstract: This update report gives an overview of the modeling effort to date, including a summary of the results from the phase-one study using two-dimensional models and plans for the phase-two study involving three-dimensional modeling of chip-scale packages. Using the preliminary models, it was observed that for the range of die attach, overmold, and substrate materials considered, no significant change in the plastic work density per cycle in the solder was observed. Also, for the range of die thickness, substrate thickness, pad diameter and via diameter considered, only slight changes were observed in the plastic work density in the joint. Finally, although the response was dependent on the substrate, it was consistently observed that a high modulus, low thermal expansion overmold material is desirable for reducing the plastic work density per cycle in the solder joint.

Site Redressing – Rework Of Chip Scale Packages
Authors: Ashish Alawani, Parvez M. S. Patel and K. Srihari
Abstract: Once a Chip Scale Package (CSP), or for that matter any area array package, is removed in a rework process, the site must be cleaned in preparation for a new package. The goal is to effectively remove the residual solder without damaging the solder mask material and/or lifting the pads. Currently, two methods are commonly used for the removal of residual solder. They either use a vacuum de-soldering system or a soldering iron with a solder wick. These are manual site-cleaning methods. An automated site cleaning system called the “scavenging system”, is provided on the rework system used in the research. The aim of this study was to establish a comparison between the different site redressing options. In addition to this, the scavenging tool, provided into the rework station presently being used for research, was characterized and subsequently compared to the conventional method of cleaning with a solder wick.

Rework Of Chip Scale Packages- Test Plan For Reliability Of Reworked Components
Authors: Parvez M.S. Patel and K. Srihari
Abstract: The aim of any rework operation is to obtain assemblies that have reliability as good as, if not better, than non-reworked assemblies. The entire rework process for the rework of Chip Scale Packages was developed at the Universal Instruments Corporation, Surface Mount Technology Laboratory. This involved component removal, site redressing, solder replenishment and component replacement. Having successfully obtained reworked assemblies, the next step was to evaluate their reliability and comparing the same with non reworked assemblies.

The following report explains the various testing methodologies that can be used to evaluate the reliability of Surface Mount Assemblies. Finally the various factors affecting the reliability are discussed.

Reliability Modeling Of Chip Scale Packages
Authors: James M. Pitarresi, Bala Nandagopal and Sundar Sethuraman
Abstract: A finite element based approach for estimating the thermal cycling reliability for chip scale packages is presented. The methodology is based on Anand’s viscoplastic constitutive law for the solder response and Darveaux’s crack growth rate model for solder fatigue. A Weibull two-parameter failure distribution is assumed. Three-dimensional finite element models were built for each of the sixteen packages studied. The number of cycles to fifty percent package reliability was estimated for two different thermal profiles. Good correlation between the measured and predicted life was observed for the four packages that have completed their testing. Each of the package’s measured life was within the expected 1.5X resolution of the method. A limited number of parameter studies were performed using the three-dimensional models. It was observed that increasing the flexibility of the elastomer layer in flex-based devices resulted in a higher joint life while a larger via size and decreased die thickness both produced a modest joint life increase.

Rework Of Chip Scale Packages- Component Removal Process
Authors: Parvez M.S. Patel and K. Srihari
Abstract: Chip Scale Packages (CSP) technology offers robust packages with small footprint and high interconnect density. However, one drawback to CSPs and also to BGAs is the difficult rework process compared to peripheral leaded surface mount devices or through hole components. The four main steps in the rework of any Area Array component are component removal, site redressing, solder replenishment and component replacement. Careful thermal profile development, rigorous process control and proper equipment selection can greatly improve the CSP rework process.

Component removal involves nondestructively removing the damaged component by heating the solder to a temperature above liquidus. In this process, some of the major concerns are obtaining a proper thermal profile to avoid warpage, minimizing component and board damage and avoiding damage to the adjacent components.

The aim of this study is to develop profiles and to establish a robust removal process that can be generalized for reworking CSPs, keeping in mind the process variables and available resources.

Rework Of Chip Scale Packages- Component Replacement Process
Authors: Parvez M.S. Patel and K. Srihari
Abstract: After the defective CSP has been successfully removed using the component removal process, the steps that follow to complete the rework process are site redressing, solder/flux replenishment, and component replacement. The site redressing operation should remove most of the residual solder left on the reworked site, providing a coplanar solderable surface. Subsequent solder/flux replenishment process will provide the necessary solder required for a solder joint that is electrically and mechanically sound. The component replacement process follows, which is the most important step in determining the yield of the rework process and the reliability of the reworked component. The aim of this study was to evaluate different solder replenishment processes, to develop profiles that can be used for replacement and to establish a robust replacement process. Some results obtained were:

  • For pitch sizes more than 0.75mm, Mini Stencil printing is perhaps the most simple and fast method of solder deposition for rework involving minimal cost.
  • For pitch sizes less than 0.75 mm, flux application is more practical than solder paste application.
  • Manual dispensing showed large amount of bridging across the pad sites. It becomes extremely difficult to dispense precise amounts of solder paste for fine pitch CSPs.
  • The temperature profile that can be used for component removal as well as replacement was successfully developed.
  • Higher standoff, approximately 1.5 to 2 mils more was observed for samples that used solder paste for replacement, than those using flux.
  • The use of nitrogen atmospheres reduces the chances of solder balling, reduce the flux residues and minimize the oxidation of solder during reflow.

Evaluation Of Csp/Dca Test Board-2
Authors: Parvez M.S. Patel, Suresh Jayaraman and K. Srihari
Abstract: The development of very complex Integrated Circuits (IC) with high input/output counts coupled together with steadily increasing clock rates have forced the electronics manufacturer to develop new packaging and assembly techniques. Components with pitches down to 0.3 mm, BGAs, micro BGAs and flip chip technology are underlining this trend and highlight the importance of new Printed Circuit Boards (PCBs) that are able to cope with these recent and emerging requirements. It becomes necessary that the PCBs used for such assemblies meet the requirements of electrical, dimensional, thermal and mechanical properties.

This is a report on the characterization of the test vehicle, CSPTB-2, used in the consortium, and presently being supplied by different vendors. Particular attention is given to the assessment of pad sizes, masks registration, pad geometries, their metallurgy and surface finish and the various defects and nonconformities observed therein.

A comprehensive study of the various surface finishes and the plating technologies was done as part of the literature survey. Measurements were carried out to study the following board parameters:

  • The vendor -to- vendor and board to board variation in pad diameters.
  • Vendor -to- vendor and board to board variation in the difference between the centers of the solder mask windows and the centers of the pads in terms of the mis registration.
  • The vendor to vendor and board to board variation in mask diameters.
  • Any variation, if present on the board build up.
  • A detailed study of the pad geometry.
  • Any other defects if observed.

The results are then discussed in light of the design values and their effects on the reliability and related issues.

Csp Dca Consortium Test Vehicle # 3
Author: Anthony Primavera
Abstract: Assembly of chip scale packages (CSP) are becoming more common for memory and control applications. Investigation of the robustness of CSP assembly onto organic printed circuit boards (PCB) has been investigated at Universal Instruments Corporation as part of the CSP Consortium. Design considerations for CSP and DCA applications are considered paramount for this project. As technology drives CSPs and flip chip development, the PCB technology must keep pace in order to efficiently use the smaller components. The board is one of the most important parts of the assembly since it not only provides the mechanical support and joining attachment pads, but it mainly serves as the interconnection pathway for components mounted on the board. Flip chip and CSP area array devices are challenging the board industry to provide a technical solution to the routability of small devices yet the overall price of the system must remain controlled. Micro via techechnology is one fabrication method that allows interconnection of the outer layers of the board with the adjacent layers of the board without the need of a plated through hole. The vias can be created by several methods including laser, photolithography or by a plasma reactive gas. Several considerations of this technology include via size, spacing, required capture pad or annular ring around the via, and the dielectiric material in which the via is formed. CSP/DCA Test board 3 was designed with both conventional surface trace circuitry as well as microvias for routing of the circuit daisy chain interconnections.

Stencil Printing On 200″M & 250″M Pitch Pads In A 3 Row Perimeter Array
Authors: Jeffrey D. Schake and K. Srihari
Abstract: A series of SGS Thomson FC6 wafers were bumped by stencil printing utilizing three stencil designs and two different stencil vendors. Stencils were produced with a variety of oblong, rectangular, circular, and square shape apertures in order to compare the differences in the resulting transfer efficiencies and corresponding bump distribution scatter. It was found that the aperture area ratio accounts for most of the influence on the resulting bump size rather than aperture shape. However, for equivalent area ratio apertures the oblong gave a higher transfer efficiency than the rectangle, and the square did slightly better than the circle. In terms of bump scatter, there was no observed dependence on aperture shape. There was a notable dependence on stencil manufacturer. Another significant discovery was the impact of a delay period between the printing stroke and release process. This led to a significant reduction in bridging defects. Further statistical tests were conducted on the measured bump height data to compare the influences that stencil design attributes and printing conditions have on these bump distributions.

Stencil Technology Evaluation
Authors: Ashish Alawani, Anthony Primavera and K. Srihari
Abstract: Stencil printing solder paste is a critical process in assembly of Electronic components onto printed circuit boards in surface mount manufacturing. The stencil design and characteristics drastically affect the resulting print quality of the deposited solder paste. Several key parameters affect print quality and assembly defect rates. The key parameters include aperture shape and design, the size of the apertures, aperture wall shape, roughness, accuracy and repeatability of feature size and position and finally material selection. In an attempt to characterize the print process or reduce or eliminate assembly defects, a thorough evaluation of stencil technology for fine pitch printing is required. This report investigates the current manufacturing techniques, and discusses pertinent, critical issues.

Reliability Testing Results For Chip Scale Packages
Authors: Robert Fenton and Michael Meilunas
Abstract: A chip scale package (CSP) is a device that typically has a package to die dimension ratio of less than 1.2 (i.e. the package is <20% larger than the die). Also, the definition of a CSP has been such that it includes area array components with lead pitch of 1.0mm or less. Universal Instruments was involved in the reliability testing of CSPs with an emphasis on second level reliability. The failure mechanism of primary concern is solder fatigue damage that results from the inherent differential thermal expansion between the component and printed circuit board (PCB). In this research, air to air accelerated thermal cycling was used to evaluate package reliability. Factors investigated include PCB characteristics such as thickness, surface finish and pad size; assembly conditions including the reflow atmosphere, fluxing agent (paste or flux) and double sided simulations. Package characteristics were also tested and included: die dimensions, package size, substrate materials and mask opening dimensions. Testing was conducted at several sites under various conditions to include 0 to 100ºC, -40 to 125ºC, -40 to 100ºC and -55 to 125ºC cycles. The purpose of this project was to identify the dominant factors affecting CSP reliability and the modes of failure these factors invoke.

“Overview Of Test Structures Designed Into Microvia Test Vehicle, Csp Tb-3”
Authors: Anthony Primavera and Suresh Jayaraman
Abstract: A test vehicle, CSP TB3, was designed primarily for the evaluation of the reliability of microvia interconnect structures. This also proves as a means to evaluate the capabilities of the various via formation technologies with respect to minimum via size and the thermal cycle reliability. This report provides a detailed description of test vehicle design and construction. The test board also contains high density Chip Scale Package (CSP) and Direct Chip Attach (DCA) component sites, some of which are routed using microvias in component pads. All the component sites in the test board are explained in detail. In addition to the microvia chains (present on the topside), the bottom side of the test board also contains structures for testing the dielectric strengths of the microvia buildup layers. Also included in the report, are the factors affecting the reliability of microvias.

Evaluation Of Csp/Dca Test Vehicle – Iii
Authors: Suresh Jayaraman and K. Srihari
Abstract: Trends in miniaturization and silicon integration have placed additional pressure on printed circuit board technology. Conventional printed circuit board technology is reaching its limit for the interconnection of new area array devices such as Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs) and flip chips. Plated Through Hole (PTH), that is used to make to the layer to layer interconnections in conventional circuit boards, use up valuable trace routable area even in layers not intended for interconnection. Microvia technology and high density circuit boards with built up multilayers are being aggressively developed to address routing issues associated with the new area array devices.

CSP/DCA Test Vehicle-III was designed the reliability of microvias. Further, component sites were designed with microvias in pads to evaluate the reliability of the solder joint on a microvia. CSP/DCA TB-3 was obtained from three vendors offering different via formation technologies. Boards from vendors E and V had laser-drilled vias, while vendor W supplied boards with photodefined vias. This report presents the results of the characterization performed on the test boards from the three vendors. The pad diameters, mask openings and the pad-to-mask misregistration was measured at a CSP site (64 I/O, Full Area Array on a 0.8 mm pitch) for three vendors. The board build-up technologies and the dimensions of the multilayers have been compared and contrasted for these three vendors. Further, the microvia diameters and resistance values were measured for the different via sizes for all three vendors that have supplied vias manufactured using different technologies and materials.

Evaluation Of Reliability Of Microvias And Failure Analysis
Authors: Suresh Jayaraman and K. Srihari
Abstract: This report presents the results of the reliability evaluation performed on the microvia interconnect structures that were designed into the CSP/DCA Test Vehicle III. The reliability of the microvias was tested by subjecting the microvias to Liquid-To-Liquid-Thermal Shock (LLTS) testing. These vias were formed using different technologies and using different build up materials by three different vendors. The vias were initially cross sectioned (as received) to evaluate the shape and the structure of the vias formed by the various technologies. The via resistance were also measured before the samples were sent for LLTS testing. The via chain resistance and continuity was measured after 100 LLTS cycles. Subsequently, the failed samples were cross sectioned to assess the possible causes for the via failures.

Quantification And Elimination Of Systematic Variations In Solder Paste Printing
Authors: Chih-chun Chang and K. Srihari
Abstract: Statistical variations in solder bump heights across an array may combine with component and substrate variations to strongly affect CSP and DCA assembly yields. Statistical analysis of solder paste printing data for stencils with area arrays of large, circular apertures showed the volume distributions to have significant systematic components. An analysis is outlined, allowing the quantification of these contributions. Based on this, stencils may be redesigned to reduce the scatter, and/or assembly yield predictions may be greatly improved.

Dca Project Overview
Author: Peter Borgesen
Abstract: The present report is intended as a comprehensive overview of the DCA Consortium project. Discrepancies between this and the progress reports are ascribed to us getting smarter with time after all. References are made to all the existing progress reports, but the present text should be sufficient to many. One way or the other, it is recommended to always start from this.

Recognizing the reluctance of many to read even the present number of pages this report is structured in many small, specialized sections with cross references so that a particular subject can be pursued without starting from one end. In fact, initial insight into a particular topic will often be achievable by reading less than 5 pages!

An Overview Of Electrically Conductive Adhesives
Authors: V. Muthiah and Anis Zribi
Abstract: Conductive adhesives have been used for electronics packaging applications for years in certain hybrid, die attach and display assemblies. The environmental incompatibility of the lead in tin-lead solder, has triggered a growing interest in electrically conductive adhesives as an alternative within the past decade. Like many other new technologies, conductive adhesives have certain beneficial characteristics as well as characteristics that require improvement.

This report presents an overview of the current status of the conductive adhesive bonding of flip chip assemblies. It is a compilation of available literature on conductive adhesives. The different issues relating to the conduction mode, types of conductive adhesives, vendors, assembly techniques, and required equipment for assembly have been outlined. The different assembly procedures used by different companies and research organizations are also detailed. The various reliability concerns and the novel materials being developed to address these concerns are also documented.

Process Summary & Guidelines For Bumping Wafers By Stencil Printing Of Solder Paste
Author: James H. Adriance
Abstract: The process of bumping wafers by the stenciling of solder paste has been researched at Universal Instruments Corporation for the last two years. The intent of this document is to provide a design guide, summarizes the process that has been developed to date and to provide some insight of future development. This wafer bumping process is based on a technique of “over printing” solder paste onto wafers with the use of a metal mask stencil. The term “over printing” is used because the solder paste deposits that are printed onto the wafer are always larger than the attachment pads. Standard solder paste stenciling techniques are used to deposit the solder paste onto the wafer. The primary advantage of this wafer bumping process is that it does not require any type of masking process for each individual wafer. The elimination of the masking process reduces the number of steps in the process as well as the cost of the process. The major steps in this wafer bumping process consists of stenciling of the solder paste directly onto the wafer, optional inspection of the solder paste, mass reflow of the solder paste, followed by post soldering flux residue removal by the use of DI water. Any under bump metallization that provides a solderable surface may be a candidate for this bumping process. Electroless Nickel\Gold and un-protected Copper (as a final metal layer) have been tested to date. Further research will continue to better understand the capabilities and robustness of this wafer bumping technique. Improvements in stencil and solder paste technology will enable this bumping technique to increase in capability as well as robustness. Stencils and solder paste coupled with their associated technologies are the two major variables that will provide the greatest improvement to this wafer bumping technique.

Board Bumping Of Ibm Surface Laminate Circuit Tm Substrates By Flip Chip Screen Printing
Authors: Miguel Jimarez and Jim Adriance
Abstract: When attaching integrated circuits (ICs) with high Lead bumps i.e. Flip Chips (FCs) to organic substrates, a lower melting alloy is required. Eutectic or close to eutectic tin & lead alloy is the most common type of solder alloy used. A few different methods are used to apply the solder alloy to the substrate attachment pads. In some processes the lower temperature solder alloy is deposited directly to the high lead bump on the IC instead of the substrate attachment pads. Some of the methods used to apply the solder alloy to the organic substrate attachment pads are electroplating, solder injection, bump transfer and solder paste printing techniques. The main objective of applying the solder alloy to the substrate attachment pads is to obtain a given solder volume, which is repeatable for all the attachment pads. Incorrect solder volumes (too little or too much) and/or inconsistent solder volumes may produce assembly yield problems and/or reliability problems. Each of the processes mentioned have their advantages and dis-advantages. Factors such as cost and manufacturability are generally the most critical factors used to select a given process.

This work focuses on applying the technique of stencil printing solder paste (Flip Chip geometry’s) to Surface Laminate Circuit TM (SLC) substrates (single image and 4-up strips) that contain FC footprints. The process includes the printing step, mass reflow, post reflow flux residue removal and flattening (coining) of the solder bumps. The printing was done over several days to ensure set up and day to day variability as well as, to explore manufacturability. In all, 749 laminate chip carrier SLC Test Vehicles (TVs) were printed, 204,477 bumps. It is planned to assemble and test the bumped laminate chip carrier SLC TVs to correlate printed volumes to assembly chip attach yields and reliability results.

The Effect Of The Separation Speed Setting On Solder Paste Printing
Authors: Santhana S. Satagopan, Jeffrey D. Schake, Yan Sha and K. Srihari
Abstract: The so-called separation speed is believed to affect the shape of the individual deposits during solder paste printing, and rumor has it that it may affect the deposited volume as well. Indeed, model experiments showed a sensitivity to the rate at which aperture and substrate are separated, although only within a relatively narrow range of aspect ratios. However, it is argued that the effective separation speed in a real stencil printer is not as controllable as suggested by the machine settings, because of deformation of the stencil during paste release. The effect of the nominal separation speed on the solder deposition was therefore investigated for different pastes and various stencil aperture sizes and shapes. In general, the machine setting is found not to affect the average volume transfer significantly. However, within the narrow regime where the transfer ratio varies strongly with aperture aspect ratio, the nominal separation speed does have a moderate effect on the width of the volume distribution and the shapes of the individual deposits.

Aperture Filling In The Solder Paste Stencil Printing Process
Authors: Jeffrey D. Schake, Yan Sha and K. Srihari
Abstract: It is anticipated that a general, mechanistic understanding and model of the stencil printing process may help controlling and predicting the solder volume distributions across the die, wafer or printed circuit board. It is here emphasized that the scatter across an individual die or die region may often be even more important than the absolute volumes. The present experimental study is intended to help develop a phenomenological picture of one part of the process, the filling of the stencil apertures.

It is found that the individual aperture is filled to about 10% by the front part of the solder paste bead, while the remaining part of the filling occurs near the squeegee tip, where the internal pressure is much higher. The printing results are thus expected to depend on the rheological properties of the solder paste under high pressure and, presumably, high shear. The potential consequences for the characterization and understanding of the process are outlined.

Solder Paste Release From Real And Scaled-Up Stencil Apertures
Authors: Jeffrey D. Schake and K. Srihari
Abstract: The deposition of solder paste by stencil printing is attractive because it is relatively inexpensive. The process is, however, sensitive to a large variety of experimental parameters, particularly for fine pitch applications. Striving to deposit larger volumes at finer pitches, we are primarily limited by clogging of the stencil apertures, i.e. by difficulties in paste release rather than in aperture filling. Narrower apertures and/or thicker stencils invariably lead to clogging and, before that, to an increased scatter in the deposited volumes.

The paste release process was investigated using both stencil printing and scaled-up experiments. The process was seen to depend on aperture and paste material, aperture shape, and separation speed in a somewhat systematic fashion. Not all of these dependencies are, however, of importance for applications.

Stencil Printing On A 6-Mil Pitch Staggered Perimeter Array
Authors: Jeffrey D. Schake and K. Srihari
Abstract: The printing of a Type V solder paste through 5.5-5.9 mil wide apertures on a 6 mil staggered pitch in 3 mil thick stencils was investigated in terms of the volume distributions of reflown solder bumps. Longer apertures were found to lead to significantly taller bumps and reduced scatter. Numerous statistical tests were conducted to identify the effects of stencil parameters and printing conditions. Factors found to be significant include stencil quality (aperture size variations), aperture size, aperture area ratio, aperture orientation and stencil foil orientation. The factors were not all independent.

On The Release And Printability Of Solder Pastes With Different Metal Contents
Authors: Sandeep Tonapi and K. Srihari
Abstract: The influence of metal content (88 – 92%) and temperature (16° C, 24° C and 32° C) on solder paste release was studied through a series of experiments. A scaled-up aperture was used to represent the release phenomenon in stencil printing. In addition, a solder paste slump test and a printability evaluation were also carried out. This research indicated that temperature affects the release properties of solder paste for the different metal contents considered. The slump test gave an indication of the limits at which a solder paste with a particular metal content will result in solder bridging. The printability experiments indicated that as the metal content increased, the print quality improved. Delay time had an adverse effect on all the five pastes considered.

Rheometry Of Solder Pastes
Authors: William J. Walker, Jr. and William M. Carty
Abstract: For rheological measurements on solder pastes to be useful in establishing correlations with printing performance, they need to be reliable, reproducible and descriptive of actual material properties. The limited success of previous rheological studies may partly be ascribed to the data collection methods.

The present report describes measurements of solder paste and unfilled flux performed using both a stress controlled rheometer and a strain controlled rheometer. Differences were observed between the two instruments for shear thinning behavior of both flux and solder paste because of the different shearing conditions imposed by each instrument. Creep measurements indicate that a number of different relaxation phenomena are present in solder paste. Dynamic measurements on the stress-controlled rheometer indicate that the linear viscoelastic range of these materials is small, and dependent on the shear history of the material.

Correlations Between Solder Paste Rheology And Printing Performance
Authors: William Walker, Donghun Lee and William M. Carty
Abstract: This project investigated the rheology of solder pastes for stencil printing applications culminating in the construction of a rheological process control diagram which should be useable for predicting stencil printing behavior. To construct the diagram, a series of experiments were conducted, including: 1) characterization of the rheometers for taking the measurements; 2) measuring steady-state and viscoelastic behaviors of the pastes, 3) characterizing the solder particles; 4) conducting a systematic evaluation of various pastes at different temperatures; and 5) evaluating printing performance. The results of these tests were distilled into a rheological process control diagram that separates the composition of the solder paste from its performance in a printing process. It was necessary to combine both steady-state and viscoelastic data (in the form of a defined relaxation time) to develop the diagram using transfer ratio as a quantifiable measure of the printing performance. Detailed procedures regarding the experimental procedures and the construction of the rheological process control diagram are presented in the report.

Flip Chip Placement Yields
Authors: Peter Borgesen, Sanjay Sharma and Subhash C. Sarin
Abstract: Theoretical case studies were conducted to assess the placement related defect levels expected for the attachment of fine pitch flip chip to regular FR-4 and BT type substrates with solder masks. Effective placement yields were found to depend on design, substrate tolerances and placement machine accuracy. Optimized designs were identified. Yields were predicted for various levels of machine performance based on typical tolerances quoted for such substrates at moderate and fine pitches. At finer pitches, where pad sizes are necessarily reduced, defect levels increase correspondingly.

Typical solder mask tolerances usually lead to a requirement for rather large solder mask openings, and thus low standoffs, in order to ensure placement related defects on the order of 1 ppm or less. This is not very sensitive to placement machine accuracy. The low standoffs will generally affect underfill process times and materials selection and become prohibitive at pitches near and below 6 mil. In most cases the only obvious remedies would seem to be either strongly improved solder mask tolerances or a change of substrate technology. When possible a substrate design with traces through solder mask trenches that are all parallel may be an attractive alternative.

Assuming sufficiently large solder mask openings the placement yields are still sensitive to contact pad tolerances and machine accuracy. The machine performance required to ensure less than 1 ppm defects was assessed. For this purpose the machine errors were assumed to be described by normal distributions in the x- and y-directions with the same standard deviation, s m.

6, 5 and 4 mil wide contact pads would require machine accuracies of s m = 0.41, 0.35, and 0.2 mil, respectively. The use of 3 mil wide traces/pads requires either tighter pad tolerances or inspection of the substrates to ensure a minimum pad width of, say, 1 mil. Such an inspection, together with a machine accuracy of s m = 0.12 mil, would keep defect levels below 1 ppm.

Area Array Assembly Yield Program Manual
Authors: Sanjay Sharma and Subhash. C. Sarin
Abstract: The Area Array Assembly Yield Model is a tool to estimate the total number of defective joints and components for one million assemblies, as per the distribution of the input variables. Most critical parameters were identified and incorporated in the development of the mathematical model representing the assembly process. Several case studies have been done to develop the approach and the individual modules of the model have been analyzed extensively.

The Yield Model Software is an extension of the mathematical model. It provides a user-friendly front end for the determination of the yield value. The program presents a series of input screen and context sensitive help on individual forms. Yield calculations are performed in different modules based on the selections done by the user. The software has a combination of option button, check box and input box that prompts the user for information. This report is a user’s manual, and contains discussion on topics such as the software architecture, concepts, input screens and system output.

The use of software does require a prior knowledge of the characteristics of the CSP or DCA package and assembly process. The program has an in-built ability to check for input values and suggest changes via error or information messages.

Area Array Placement Yield Prediction
Authors: Manikandan Munikrishnan and K. Srihari
Abstract: The knowledge of placement yield of an assembly process is very important for development of the process and to make strategic decisions regarding the equipment required. The present report describes a Monte-Carlo simulation program, which predicts the number of defects occurring during placement of an area array device, based on user supplied statistics for in-plane substrate variations and machine accuracy. The repeatability of the program has been tested and the range of total number of errors is equal to the square root of the total number of errors. This report is a user’s guide for the application and also discusses the assumptions made in the simulation model.

On The Application Of Reflow Encapsulants To Dca Assembly
Author: Pericles A. Kondos
Abstract: Several reflow encapsulants from Kester and Emerson & Cuming were used in assemblies with different die and board types, and the results were tested for the quality of soldering and for bubbles and voids before and after reflow. Many other model experiments were performed with the same encapsulants, mostly to study the reasons and the parameters affecting bubble formation.

It was seen that bubbles always formed during encapsulant dispensing and die placement. Heating the encapsulants at “soaking” temperatures in the neighborhood of 150°C causes rapid dissolution of the bubbles. Virtually all the bubbles existing in the encapsulant after placement are small enough to be expected to vanish during reflow, unless gas from other sources either enters pre-existing bubbles or forms new ones. The proper combination of encapsulant, board preparation, and reflow profile, led consistently to essentially bubble-free results; in other cases, elongated and narrow voids appeared instead of (or in addition to) bubbles after reflow.

Die floating and movement after placement can be avoided by holding the die in place for sufficiently long time, allowing the material to wet the sides of the die.

Premature onset of curing for some encapsulants occasionally prevented good soldering. Modifying the reflow profile did not completely solve this problem.

The Kester 9101 performed best in these tests, with respect to bubble avoidance, minimizing die floating, and soldering. The E & C 54-4 also showed promise. The assembly parameters have not been optimized for any of these materials, and further tests are necessary.

Evaluation Of Polymer Flip Chip Assembly
Authors: V. Muthiah and Anis Zribi
Abstract: Electrically conductive adhesive interconnect technology is emerging as a potential replacement of lead based soldering. This report conducts an initial evaluation of the feasibility of using the Polymer Flip Chip (PFC) process to attach 8 mil pitch die to regular FR-4 boards. Screening experiments identified a set of print parameters that produced consistently good prints of the conductive adhesive on to FR – 4 boards with pads in 8 mil wide solder mask trenches. These print parameters were used to assemble a set of die which were underfilled using Epoxy Technology’s U300. Different assembly issues observed during experimentation have been documented. The various reliability concerns while implementing the PFC technology have also been reported.

Assembly Process Development For Large Area Array Flip Chips (Amkor Anam Build)
Authors: Vinu Yamunan and K. Srihari
Abstract: The assembly of large fine pitch flip chips onto organic substrates is a complicated process. The development of a robust assembly process requires a thorough examination of all factors that affect the process, its yield as well as the final product’s reliability. The complexity of the situation is multiplied because of the interdependence and interactions between the several factors in the system. This research effort focused on the development of the assembly process for a large (432 mils square) flip chip with 582 Input / Output (I/O) interconnects arranged in complex area array patterns. The placement process was optimized for these dies onto thin (20 mil) organic substrates and the flux application process was set up to compensate for the tolerances in the solder bump heights on the dies. This research also examined issues that affected the assembly yield and systematically developed solutions for them. These issues included the quality of bumping and problems with fiducials, soldermask misregistration and the die site design. After development, the process was validated by assembling a small batch of 252 dies in the laboratory with low defect levels. These assemblies will now be used for experimentation on material selection for improved reliability of the chip-encapsulant adhesion when subjected to temperature cycling.

Effects Of Moisture Exposure Before Reflow On Flip Chip Reliability
Authors: Vinu Yamunan and K. Srihari
Abstract: Previous research showed outdiffusion of moisture from the substrate during early stages of encapsulant cure to affect subsequent delamination in thermal shock. Current guidelines suggest that DCA assemblies should be baked out before underfulling if they have been exposed to ambient humidity for a total of more than 8 hours. This has serious consequences for demands on process control and/or convenience (cost).

The present report addresses three questions: (a) Is exposure before reflow much less critical than exposure after? (b) Would a faster curing encapsulant allow for a broader process window? (c) Does the enhanced delamination actually affect the rate of electrical failure? Experiments were conducted with two different encapsulants (Hysol FP4511 and Namics 8437-2) under 8 mil pitch nitride passivated flip chips assembled onto 62 mil thick FR4 substrates. Potential local effects of solder mask openings exposing the underlying laminate were assessed by comparing sites with and without solder mask.

Assembly Of 2100 I/O High Density Flip Chips
Authors: Vinu Yamunan and K. Srihari
The present effort dealt with the assembly of large, fine pitch area array flip chips (2100 I/Os) on organic substrates. An assembly process was developed for 6 mil pitch area arrays. The large number of the joints and the low standoff pose particular problems. The flux application process and the impact of bump height distributions on this and the rest of the assembly process were discussed. Two fluxes and three encapsulants were considered.

Assembly Process Development For 4-5 Mil Pitch Flip Chip On Fr-4 Boards
Authors: Vinu Yamunan and K. Srihari
Abstract: Assembly processes were developed for the attachment of fine pitch flip chip to 62 mil thick FR-4 substrates by systematically addressing material and process issues. Particular emphasis was placed on die with 130mm pitch single perimeter arrays and 128mm pitch double perimeter arrays. Preliminary work was, however, also done on a 102mm pitch single perimeter die.
Bump height distributions characterized with the WYKO bump measurement system were used in the development of the flux application process and for the assessment of manufacturability. The flux film thickness, dip time and the rate of retraction of the die from the flux film were all found to affect the formation of flux bridges between adjacent bumps. Tests showed Kester TSF 6502 to be the most suitable because of its (lower) viscosity. Offsets as large as 1.5 mil, presumably caused in handling, were completely eliminated by the self-centering action in reflow and good joints were formed. The 102mm die appeared the most robust against flux bridging probably due to the ellipsoidal, as opposed to the usual spherical, shape of these particular joints.

Effects Of Flux Type On The Reliability Of Flip Chip Encapsulation
Authors: Vinu Yamunan and K. Srihari
Abstract: The application of liquid and tacky fluxes onto flip chip solder bumps differs in the techniques used as well as in their impact on the reliability of the encapsulated flip chips. Water-soluble fluxes present the additional necessity to clean the assembly prior to underfilling. Also, the cleaning operation becomes more difficult as the die size increases because of the inaccessibility of the areas under the die. This work compared the reliability of flip chips assembled using three different fluxes (Alpha WSF 856 – Liquid water soluble flux, Alpha NR 205 – Liquid no clean flux and Kester TSF 6522 – Tacky no clean flux). The die built using water-soluble fluxes showed an evident degradation in the reliability indicating the presence of flux residues and their effect on the adhesion at the chip-encapsulant interface. The performance of the assemblies was monitored by means of electrical testing as well as acoustic microscopy. Increased delamination and rapid failure of the electrical networks was observed for die built using the water-soluble flux (Alpha WSF 856).

Effects Of Encapsulant And Flux Type On The Thermal Shock Resistance Of Dca Assemblies
Authors: Udayabhaskar V. Putcha and K. Srihari
Abstract: The reliability of a Direct Chip Attach (DCA) assembly depends on a wide range of design parameters, including the die passivation, encapsulant, flux, board pad metallurgy, board thickness, and soldermask. While the fatigue and failure of the solder joints is clearly affected by encapsulant delamination, it also depends on some of these parameters directly. Substrates with Ni/Au-coated copper pads may lead to weaker solder joints, and thus faster electrical failure, than OSP-coated pads, to the extent that such joints have been seen to fail without significant encapsulant delamination. Also, a change in board thickness has been seen to substantial, and partly independent, changes in delamination and electrical failure rates.

In the present effort ¼” nitride passivated die were attached to 62 mil thick FR-4 boards with OSP-coated pads, using one of four different no-clean fluxes, and underfilled with one of five different encapsulants. The assemblies were then subjected to Liquid-to-Liquid Thermal Shock (LLTS) and the resulting encapsulant delamination and electrical failure monitored. As both chip passivation and solder mask type are known to affect adhesion at the encapsulant-passivation interface, the effect of varying both was also briefly investigated.

The Impact Of Flux Types On Flip Chip Assembly
Authors: Vinu Yamunan and K. Srihari
Abstract: Different flux application techniques have different effects on the assembly process for flip chips as well as the performance (reliability) of the assemblies. This research investigated the effects of different flux types (liquid – water-soluble versus no clean) on the assembly process for flip chips on organic (BT) substrates. The observations made in this experiment revealed that liquid (no clean and water-soluble) fluxes, despite their reasonable performance, are not robust. Tacky fluxes perform better than the liquid fluxes with respect to handling of assemblies while performing comparably in terms of solderability. Water-soluble fluxes require additional cleaning operations and are therefore unattractive options.

Die Cracking In Direct Chip Attach Assemblies
Authors: Robert Erich, Udayabhaskar Putcha, Yan Sha and K. Srihari
Abstract: Die cracking has been observed during both handling and thermal shock testing of Direct Chip Attach (DCA) assemblies. So far, the phenomenon has been most reproducibly observed in thermal shock testing. The phenomenon is found to be dominated by horizontal cracking, i.e. a crack starts from the edge of the die and propagates parallel to the silicon surface. It is believed that these cracks are caused by edge defects which are most likely introduced during dicing. Indeed, the performance was greatly improved by reducing the dicing induced defect levels. Simple 3 point bending tests did not reproduce the observed failure mechanism, but an alternative mechanical test was developed that did.

“Effects Of Die Size, Pad Metallurgy And Encapsulant-Flux Combinations On The Reliability Of 6 Mil Pitch Dca
Assemblies”
Authors: Anis Zribi and Daniel Blass
Abstract: The electrical failure of a DCA assembly during thermal excursions depends on both solder joint properties and encapsulant delamination. The latter again is sensitive to a very large number of parameters including solder joint pitch, layout, standoff, die passivation, flux residues, solder mask, substrate thickness, underfilling and fillet defects.

The present considered the reliability of 6 mil pitch DCA assemblies with less than 1 mil standoff for 3 different die sizes, 2 board pad metallurgies, 3 encapsulants and 2 fluxes in Air-to-Air-Thermal Cycling. The very small standoff led to increased voiding and concerns as to filler distribution and general underfill quality as die sizes increased from 0.275″ to 0.825″. However, none of this appeared to contribute to the observed die size dependence. As expected the low standoff led to shorter lifetimes. Dependencies on flux, encapsulant and board pad metallurgy were, however, in good agreement with trends observed previously for larger standoffs and other tests.

Effects Of Moisture And Aging On Dca Reliability
Author: Daniel L. Blass
Abstract: This experiment examines the effects of aging and moisture on Direct Chip Attach (DCA) reliability. DCA assemblies were built with three die from Delco, Sandia National Labs, and Digital Equipment Corp. (DEC) and underfilled with Hysol FP4511 or Ablestik XP-032395-6. Some assemblies were subjected to Liquid to Liquid Thermal Shock (LLTS) reliability testing after being built. The remaining assemblies were stored/aged in ambient conditions for 18 months followed by LLTS reliability testing.

For both the new and stored assemblies, LLTS caused delamination that generally started around the solder joints. The stored assemblies, however, delaminated much sooner and this lead to faster electrical failure. Delamination was severely accelerated for the polyimide passivated Sandia die with high levels of delamination after just 25 LLTS cycles.

The accelerated delamination was attributed to the long exposure to ambient moisture. The moisture appears to have further weakened adhesion around the solder joints where the flux residues are located. Adhesion away from the flux residues was not strongly appear affected by the storage period.

Reliability Of Delco Dca Assemblies In Air To Air Thermal Cycling
Author: Daniel L. Blass
Abstract: This experiment examined the reliability of Delco die attached to 62 mil thick FR-4 boards in Air to Air Thermal Cycling (AATC). The results were compared to Liquid to Liquid Thermal Shock (LLTS) data.

DCA assemblies were built with a Delco die that measured 220 x 250 mils. The die had a perimeter array of 96 solder joints and a minimum pitch of 8 mils. The substrates were 62 mil thick FR-4 with 8 mil solder mask trenches and Cu/Ni/Au or Cu/OSP (Entek Plus) pad metallurgy. The standoff height was 2.0 – 2.5 mils. Three encapsulants and two no-clean fluxes were investigated. One flux was an experimental epoxy-based flux.

One encapsulant performed better than the other two, leading to fewer electrical failures and less delamination. Reliability was best with the epoxy flux. Assemblies with Cu/Ni/Au pads had more delamination and electrical failures occurred at a faster rate than for Cu/OSP substrate pads. Delamination generally originated at the solder joints. In a few cases delamination originated at the die corners. This was associated with cracking of the encapsulant fillet at the corners.

Small encapsulant voids formed in the solder mask openings during underfilling. Solder extruded into these voids during thermal cycling. The distance between solder joints was small enough for extrusions to form bridges between solder joints. Solder extrusions were observed for every material combination.

The LLTS results were generally similar. The same material combinations performed well. Cu/OSP pads gave less delamination and fewer electrical failures. The same encapsulant had less delamination and fewer electrical failures. Delamination generally originated in the same locations. The same level of delamination was achieved in fewer cycles in LLTS than AATC while electrical failure was not. This means that electrical failure occurred at lower levels of delamination in AATC.

“Effects Of Die Size, Lay Out And Proximity On The Thermal Shock Resistance Of Dca Assemblies”
Authors: Manish Ranjan, Uday Putcha, Prasanna Manyem and K. Srihari
Abstract: Some parameters potentially affecting the damage and failure of DCA assemblies during thermal excursions were investigated. Different assemblies on 62 mil thick FR-4 boards with Organic Solder Protect (OSP)-coated Cu-pads were compared in terms of encapsulant delamination and solder joint failure during Liquid-to-Liquid-Thermal-Shock (LLTS). Effects of die size and die spacing were quantified using different sized die cut from wafers with the same solder bump layout and mounted in different configurations on the boards. Effects of die layout were assessed by comparing die with perimeter and full area arrays.

Effect Of Encapsulant Fillet Thickness On Corner Delamination In Sgs Thomson Dca Assemblies
Author: Daniel L. Blass
Abstract: This report examines the role of the encapsulant fillets in delamination of Direct Chip Attach (DCA) assemblies. SGS Thomson DCA assemblies with a 62 mil FR-4 substrate were subjected to 3000 cycles of Air to Air Thermal Cycling (AATC). Three encapsulant were used, Hysol FP4511, Ablestik XP-032-395-6, and Zymet X6-82-5T.

While all assemblies had delamination from around the solder joints as commonly occurs for this substrate thickness, the assemblies encapsulated with Ablestik XP-032-395-6 sometimes also had delamination originating at the die corners. Corner delamination can rapidly lead to large areas of delamination and reduced reliability.

The encapsulant fillet exerts compressive stresses on the bottom edge of the die that counteract shear driven delamination during thermal cycling. Previous research suggested two very different reasons why the compressive stresses may become insufficient to suppress corner delamination. A thinner encapsulant fillet exerts less compression and increases the probability of delamination. A second cause is cracking of the encapsulant fillet at the die corner which relieves the compression and allows delamination. Thicker fillets were more likely to crack.

The encapsulant fillets of the Ablestik XP-032-395-6 assemblies were profiled with a laser profilometer and examined for cracking. Fillet thickness was not a good predictor of corner delamination for this encapsulant. While the average fillet thickness was slightly smaller for delaminated corners, the fillets at corners with and without delamination were not significantly different. No encapsulant fillet cracking was observed. A specific cause of the corner delamination was not determined for this DCA assembly but it may be related to filler particle settling in Ablestik XP-032-395-6 or the shape of the fillet.

Effects Of Fr-4 Board Thickness On Dca Reliability
Authors: Udayabhaskar V. Putcha and K. Srihari
Abstract: The reliability of a Direct Chip Attach (DCA) assembly depends on a wide range of factors including the die passivation, encapsulant, flux, pad metallurgy, board thickness, and soldermask, as well as interactions between these. The present effort investigated the dependencies on passivation, encapsulant and flux type for die attached to 18 mil thick FR-4 boards. The preferred materials combinations were found to be somewhat different from those identified previously for die on 62 mil thick boards. The difference could be rationalized on the basis of the increased assembly warpage leading to a different failure location, and thus a different dependence on local materials properties.

Reliability Of Dca Assemblies With Very Large Die And Low Standoffs In Air To Air Thermal Cycling
Authors: Anis Zribi and Daniel Blass
Abstract: Encapsulant delamination and electrical failure in DCA assemblies have been seen to increase strongly at low standoff. On thick substrates both phenomena also tend to vary with the total number of I/O, for a given solder joint pitch and layout. Except for this, there usually does not appear to be a significant dependence on die size. A concern is, however, that very large die and low gaps between die and solder mask may lead to increasing difficulties (defects) in underfilling. The question remains to which extent this will affect reliability.

DCA assemblies with up to 1.1″ die and standoffs down to 1.5 mil were tested in Air-to-Air Thermal Cycling (AATC). Two different die sizes, two board pad metallurgies, two standoffs, three encapsulants, and two fluxes were considered. Sample sizes for individual parameter combinations were usually quite small, but apparent trends were compared to similar results for other die for validation.

Effect Of Board Pad Metallurgy On Dca Reliability
Authors: Udayabhaskar V. Putcha and K. Srihari
Abstract: The thermal shock induced delamination of the underfill from the chip passivation is known to depend strongly on the type of flux residue left over from assembly. This is reflected through a sensitivity to both flux type and board pad metallurgy, as well as to interactions between these. This may give important clues as to the chemical reactions involved.

The different delamination rates of course affect the electrical life time of the assemblies as well. Independently of this, however, the solder joint properties themselves may also be strongly affected by the pad metallurgy. Ni/Au-coated substrate pads leading to an estimated 2-3% Au in the solder joints generally cause faster electrical failure, even if the delamination rate is the same. It is tempting to simply ascribe this to gold embrittlement of the solder. However, mechanical testing results reported elsewhere may indicate other materials property changes as well.

Reliability Of Nokia Dca Assemblies
Author: Daniel L. Blass
Abstract: This experiment investigated the reliability of a set of Direct Chip Attach (DCA) assemblies on 24 mil FR-4 substrates. The DCA assemblies were subjected to 2000 cycles of Liquid to Liquid Thermal Shock (LLTS). Six combinations of four encapsulants and three fluxes were investigated. The 190 x 190 mil die was assembled on five different die sites. The die sites varied the solder mask trench width, pad geometry, and other substrate features.

For substrates of this thickness, delamination often originates at the die corners. Corner delamination was observed for each encapsulant. Encapsulant fillet cracking was observed but did not appear to be the primary cause of the corner delamination. While the Namics 8437-2, Hysol FP4526, and Alpha Metals 10R2C encapsulants also had delamination from around the solder joints, Hysol FP4511 only had delamination from the die corners and this encapsulant had the lowest average delamination.

Die cracking was common for these assemblies. For each combination of encapsulant and flux, between 22% and 55% of the assemblies had cracked die.

Encapsulant voids formed in the trench openings in the solder mask during underfilling. Solder extruded into these voids during thermal cycling but the distance between solder joints was large enough to prevent bridging between solder joints.

Encapsulant Fillets: Effects Of Fillet Thickness And Cracking On Delamination In A Nortel Dca Assembly
Author: Daniel L. Blass
Abstract: This report examines the role of the encapsulant fillet in the delamination of the die passivation – encapsulant interface in Nortel Direct Chip Attach (DCA) assemblies. Assemblies were built on a 62 mil FR-4 substrate from Nortel and underfilled with the Hysol FP4511 encapsulant. After 3000 cycles of Liquid to Liquid Thermal Shock (LLTS), some DCA assemblies had delamination of the die passivation – encapsulant interface originating at the die corners. This mode of delamination can rapidly lead to large areas of delamination and reduced reliability.

Previous research found that corner delamination can be caused by inadequate encapsulant fillets. A good encapsulant fillet exerts compressive stresses on the bottom edge of the die that counteracts shear driven delamination from the die edge during thermal cycling. The encapsulant fillet surface was profiled near the die corner with a laser profilometer. The encapsulant fillet thickness was quantified by calculating the minimum distance from the bottom edge of the die to the fillet surface.

It was expected that delaminated corners would have thinner fillets but the opposite trend was found in the present work. The average fillet thickness was larger for delaminated corners. The corner delamination appears to be caused by encapsulant fillet cracking.

Thicker encapsulant fillets do enhance the compressive stresses but also the driving force for cracking. Once a fillet cracks, the compressive stresses are largely relieved, allowing for rapid delamination of the die passivation-encapsulant interface. No corner delamination was found at corners that did not have encapsulant fillet cracking.

Presumably, the optimum fillet thickness represents a trade-off between compression and cracking. This would be materials dependent. The previous guideline that Hysol FP4511 fillets be at least 12 mils thick to avoid corner delamination may be too restrictive. No corners with 9-12 mil thick encapsulant fillets exhibited corner delamination.

Reliability Of Nortel Dca Assemblies In Air To Air Thermal Cycling
Author: Daniel L. Blass
Abstract: This experiment examines the reliability of Direct Chip Attach (DCA) assemblies in Air to Air Thermal Cycling (AATC). DCA assemblies were built with a Nortel die (245 x 245 mils) on a 62 mil FR-4 substrate. The die had a two-row staggered perimeter array of 83 solder joints. The minimum pitch was 14.5 mils and the standoff height was 2 – 2.5 mils. The variables included encapsulant, flux, substrate pad metallurgy, and solder mask opening/pad site.

Three encapsulants were investigated, Ablestik XP-032395-6, Hysol FP4511, and Zymet X6-82-5T1. Each encapsulant was used to underfill assemblies fluxed with Kester 244, a no-clean paste flux. Additionally, some assemblies were fluxed with an experimental epoxy flux, Kester KK-4-21-4. The 62 mil FR-4 substrates had Cu/Ni/Au or Cu/OSP (Entek Plus) pad metallurgy. Two styles of solder mask openings were used, 9 mil circular and 7 x 11 mil oblong openings.

The assemblies were subjected to 3000 AATC cycles and the resistance tested in situ. The earliest electrical failures were removed from cycling at 1600 cycles while later failures completed 3000 cycles. Before and after cycling, the assemblies were examined for delamination with a Sonoscan C-Mode Scanning Acoustic Microscope (C-SAM). The solder joints were examined before and after cycling with a Fein Focus x-ray imaging system.

The Hysol FP4511 encapsulant performed better than the Zymet or Ablestik-6. The FP4511 assemblies had fewer electrical failures and less delamination. In particular, the assemblies fluxed with KK-4-21-4 and underfilled with FP4511 performed well. None of these assemblies had more than 5% delamination after 3000 cycles.

Assemblies with Cu/OSP pad metallurgy exhibited better electrical reliability and less delamination than assemblies with Cu/Ni/Au pads. The combination of KK-4-21-4 flux, FP4511 encapsulant and Cu/OSP pads had no electrical failures after 3000 cycles.

Encapsulant fillet cracking at the die corners allowed delamination of the die – underfill interface. Fillet cracking was observed for each encapsulant. Encapsulant fillet cracking relieves the beneficial compression at the die corner that suppresses shear-driven delamination.

Solder extrusions formed in encapsulant voids adjacent to the solder joints. Several variables affected extrusions, including encapsulant, pad metallurgy, and the type of solder mask opening. Although the relatively large pitch prohibited extrusion bridging between joints, solder joints with extrusions were more likely to fail.

Effects Of Parameter Interactions On Dca Reliability
Authors: Udayabhaskar V. Putcha and K. Srihari
Abstract: The effects of interactions between encapsulant, flux and board pad metallurgy on the thermal shock resistance of DCA assemblies were investigated for both nitride and polyimide passivated die. Design of experiments and statistical concepts were used as a basis for the experimentation and the analysis of the data. The encapsulant, pad, flux, and two-way interaction between flux and pad were found to be the most significant factors. The die passivation type also appeared to influence the DCA package reliability. The electrical behavior of DCA components seemed to depend not only on the extent of delamination, but also on several other factors.

“Effects Of Flux Residues, Soldermask, And Moisture Exposure On Dca Reliability”
Authors: Vinu Yamunan and K. Srihari
Abstract: The use of no-clean flux in the assembly of flip chips has been recommended based on previous research (Effects Of Flux Type On The Reliability Of Flip Chip Encapsulation, Yamunan & Srihari, December 1998). This study investigated the difference in the impact of no-clean fluxes (tacky and liquid) on the reliability of flip chips. Two tacky no-clean fluxes (Kester TSF 6522 and Hereaus CL84-7360) as well as a liquid no-clean flux (Alpha NR 205) were used to assemble flip chip samples. The effects of soldermask coverage of the die site as well as exposure to moisture were evaluated. Liquid to Liquid Thermal Shock (LLTS) was used as an accelerated test method. Electrical network (daisy chain) continuity and delamination at the chip-encapsulant interface using acoustic microscopy were used to monitor the performance of the samples. The results show the Hereaus tacky flux to be less sensitive to moisture than the Kester flux. The performance of Kester flux is however, much better than the others in a moisture free environment. The disadvantage with the Kester flux was found to be its high sensitivity to moisture.

Initial Moisture Resistance Screening Of Fluxes And Encapsulants
Authors: Wilhelm Prinz von Hessen, Prasanna Manyem, Uday Putcha, Vinu Yamunan and K. Srihar
Abstract: A very limited number of DCA assemblies on thin substrates were exposed to moisture preconditioning and subsequent reflows to assess effects of different no-clean fluxes and underfill encapsulants on popcorning. All combinations of two fluxes and six encapsulants were investigated. None of the combinations led to measurable delamination after 200 hours at 30oC/60%R.H. Statistics was insufficient to prove JEDEC Level 3 performance, however.

Reflow after 48 hours at 85oC/85%R.H. led to obvious damage for a few of the materials combinations. The FP4527 encapsulant from Dexter delaminated almost completely, even in the absence of flux residues. The same was observed for the U8433 from Namics when combined with the CL84-7310 flux from Heraeus, but not when combined with the TSF 6522 from Kester. On the other hand, the CNB 742-31 exhibited significant delamination when combined with the TSF 6522, but not when combined with the CL84-7310.

No other combination of flux and encapsulant led to measurable damage so far. Further screening tests are ongoing.

Reliability Of Sandia Dca Assemblies In Air To Air Thermal Cycling
Author: Daniel L. Blass
Abstract: This experiment examines the reliability of Direct Chip Attach (DCA) assemblies in Air to Air Thermal Cycling (AATC). Assemblies were built with a die from Sandia National Labs. The polyimide passivated die measured 412 x 412 mils and was 27 mils thick. The 275 solder joints were arranged in an area array with a 20 mil pitch. The die were assembled on 62 mil thick FR-4 substrates. Two types of pad metallurgy were used, Cu/OSP and Cu/Ni/Au.

A commercial no-clean flux and an experimental epoxy flux were used for half the assemblies. For the remaining assemblies solder paste was stencil printed onto the substrate pads and no additional flux was applied. The fluxed assemblies had a 3 mil standoff while the die placed-in-paste had a 5 mil standoff. The assemblies were underfilled with Ablestik XP-032395-6, Hysol FP4511, or Zymet X6-82-5T1.

The performance of the assemblies, in terms of electrical reliability and delamination, was governed by encapsulant fillet cracking and delamination. In particular, the lower standoff fluxed assemblies underfilled with Zymet had fillet cracking and corner delamination at every die corner.

The placed-in-paste assemblies had larger solder joints that more completely filled the solder mask openings. This made it unlikely that small encapsulant voids would be trapped next to the solder joint during underfilling and very few solder extrusions were observed after cycling. The epoxy fluxed assemblies also had very few extrusions, indicating that the epoxy flux residues prevent extrusion into encapsulant voids or lead to fewer encapsulant voids around the solder joints.

The placed-in-paste solder joints had many internal voids. These solder voids did not noticeably affect reliability. Solder voids were not observed in any of the fluxed solder joints.

The epoxy fluxed assemblies underfilled with Hysol FP4511 had the best reliability despite some corner delamination. This encapsulant-flux combination did not record any electrical failures during thermal cycling and had low levels of delamination.

Effects Of Substrate Thickness And Standoff On Encapsulant Delamination
Authors: Richard Xu and K. Srihari
Abstract: Previous experiments suggested that the thermal shock and thermal cycling resistance of DCA assemblies depends quite strongly on the standoff and the substrate thickness. This was investigated for model assemblies on 18 mil and 62 mil thick FR-4 substrates underfilled with the FP4511 encapsulant and exposed to Liquid-to-Liquid-Thermal-Shock. For both substrate thicknesses the rate of delamination was seen to increase with decreasing standoff. This is not readily understood on the basis of stress analysis. The thinner substrates appeared to lead to faster delamination of the encapsulant at all standoffs, in good agreement with theoretical predictions.

On The Effects Of Water Soluble Flux On Flip Chip Reliability
Authors: Vinu Yamunan and K. Srihari
Abstract: The impact of water-soluble flux residues on flip chip reliability was found to be detrimental to the reliability despite cleaning procedures adopted (Effects of Flux Type on the Reliability of Flip Chip Encapsulation, Yamunan & Srihari, December 1998). This experiment was performed to determine if the reason for the ineffectiveness of the cleaning operation in that experiment could be the large die size (575×580 mils) and the low standoff (~2 mils). Smaller die (220×250 mils) and higher standoff (2.5 – 4 mils) were used in this experiment. The effects of moisture preconditioning by JEDEC Level III testing were also included in this experiment. The results show the samples built with the water-soluble flux to have performed as well as the tacky no-clean flux, if not better. The tacky flux was also found to be sensitive to moisture.

“Finite Element Modeling Of Dca Assemblies: Effects Of Fr-4 Board Thickness, Modulus And Cte On Encapsulant Delamination”
Authors: Yan Sha and K. Srihari
Abstract: Thermal excursions, or specifically cooling, leads to the development of increasing stresses, and eventually encapsulant delamination, in DCA assemblies on typical FR-4 boards. These stresses, and their dependencies on board thickness, were assessed by Finite Element Modeling (FEM). The predicted trends were in good agreement with experimental observations of much faster delamination, starting from a different location, in assemblies on 18 mil than in those on 62 mil thick boards. The same modeling allowed the generalization of these trends, and the prediction of dependencies on board modulus and Coefficient of Thermal Expansion (CTE). No attempt was made to predict actual lifetimes.

An Overview Of Board Build-Up Technologies
Authors: Suresh Jayaraman, Krishna Kalyan and K. Srihari
Abstract: Smaller vias and smaller pads are a critical enabling technology to achieve the Input / Output (I/O) escape for high density packages. A two fold increase in the number of holes per board is anticipated every three years. Using drilled blind and buried vias to achieve the increased density requirements is technologically viable but is commercially not justified. New processes have developed to generate smaller vias, bond pads, and finer conductor lines/spaces in order to achieve higher densities on Printed circuit boards (PCBs). The new technologies are a key element in reaching these densities in a cost-effective manner. This report provides an introductory overview of some of the via forming and board build-up technologies. A more detailed report will be available following the completion of the PCB evaluation.

Finite Element Based Predictions Of The Fatigue Life Of Plated Through Holes
Authors: Yan Sha and K. Srihari
Abstract: The fatigue life of plated through holes in printed circuit boards was predicted on the basis of a two dimensional axial symmetric finite element simulation. The effects of filling the holes with various materials were assessed, as were the effects of incomplete filling and defects. Finally, the dependence on the various dimensions were estimated and discussed.

Experimental Setup For The Reliability Evaluation Of Microvias In High Density Printed Circuit Boards
Authors: Suresh Jayaraman, Yan Sha and K. Srihari
Abstract: This report explains the test procedures for the reliability evaluation of high-density test boards. Particular attention is given to the reliability assessment of microvias since the strains induced by thermal expansion mismatch between copper and the circuit board material causes them to fail during thermal cycle testing. The effect of the geometric parameters, e.g., via wall inclination angle and metallization thickness, is assessed by micro sectioning the failed samples. The other tests included are the visual, dimensional and electrical checks. Finally, the test for warpage measurement of the test boards at room and reflow temperatures is also explained.

Reliability Of Pressurized Underfill Assemblies: Effects Of Fillet Shape
Authors: Manish Ranjan and K. Srihari
Abstract: Currently, DCA products are all underfilled by dispensing the encapsulant along the die edge(s), counting on capillary flow to complete the process. While this does allow the separate close-up dispense of vital exit fillets, if necessary, the process is far from attractive. Notably, the process is usually slow and quite sensitive to a variety of parameters. Alternatives currently under investigation include so-called reflow encapsulants and a pressurized underfill technique.

The present report describes preliminary comparisons of assemblies underfilled by the conventional approach and by pressurized underfilling in terms of voiding and thermal shock resistance. Without addressing manufacturing relevant equipment issues and process robustness it is concluded that pressurized underfilling has the potential for producing just as good assemblies. It remains to be ascertained whether this can be done reproducibly.

On Correlations Between Dca Assembly Warpage And Encapsulant Delamination In Thermal Shock
Authors: Manish Ranjan and K. Srihari
Abstract: An attempt was made to identify one of the mechanisms behind the statistics of failure of DCA assemblies on thick FR-4 boards. Variations in assembly warpage are believed to reflect both stress variations and the statistics of encapsulant cure. However, neither appeared to affect the variations in thermal shock induced delamination of the FP4511 encapsulant significantly.

Development Of The Underfill Process For 128 And 130 Micron Pitch Flip Chip Assemblies
Authors: Sandeep Tonapi and K. Srihari
Abstract: A process was developed for underfilling 128mm pitch double perimeter array and 130mm pitch single perimeter array DCA assemblies on FR-4 substrates with 6 different solder mask layouts. These fine pitch assemblies had very low standoffs, on the order of 1 mil from the top of the solder mask over the traces, offering a clear challenge to the underfill process. A systematic approach was taken. First, 11 encapsulants were tested for flow in a 1 mil gap between two glass slides. Five materials, which were found to flow relatively rapidly without voiding were then tried in actual assemblies. The two best performing ones, Dexter EH0544 and Nagase Ciba 693/R3310, were finally used in a set of assemblies currently being tested in Liquid-to-Liquid-Thermal-Shock (LLTS). First failures due to fillet cracking and delamination from the die corners were observed after 500-1000 LLTS cycles.

Effects Of Curing Ambience On Encapsulant Delamination
Authors: Manish Ranjan and K. Srihari
Encapsulant curing in air may severely affect the subsequent solderability of OSP coated copper pads in DCA assemblies. For those cases where this is a concern, curing of the encapsulant in a nitrogen atmosphere would usually alleviate the problem. The concern remains, however, as to the effect of the nitrogen on the encapsulant properties. In the present work nitrogen cure is found to improve the thermal shock resistance of three of the currently best performing encapsulants.

Systematic Analysis Of Underfill Void Formation In Amkor – Anam Assemblies
Authors: V. Muthiah, Mukul Joshi and K. Srihari
Abstract: Voids may affect the reliability of Direct Chip Attach (DCA) assemblies. Depending, among others, on location voids may allow solder extrusion which, in turn, may affect the electrical performance of the assembly. The present research represents an effort to study the effects of encapsulants and fluxes on void formation and solder extrusion. Factorial experiments, using different combinations of fluxes and encapsulants, were conducted and statistical analysis tools used to select the best choice of flux, encapsulant and the combination of the two.

Analysis Of Voiding And Jedec Testing Of Amkor-Anam Assemblies
Authors: V. Muthiah, Mukul Joshi and K. Srihari
Abstract: The reliability of a Direct Chip Attach (DCA) assembly is dependent on the performance of the underfill. The encapsulant needs to protect the assembly from the stresses that develop due to the mismatch of the Coefficient of Thermal Expansion (CTE) between the die and the substrate. Another very important issue is the voiding in the encapsulant. Voids may be sources of extrusions which may affect the fatigue resistance of the solder joints. Also, voids may eventually lead to enhanced popcorning in reflow after moisture exposure.

This research has been performed to obtain insight into the phenomenon of voiding as well as the behavior of different encapsulants in moisture. The voiding in two encapsulants (Shin Etsu 5123 and Shin Etsu 5103) in assemblies assembled with three different fluxes, Kester TSF 6522, Indium SMQ – 75, and Heraeus CL 84 – 7360, was analyzed. The assemblies were then subjected to moisture exposure followed by reflows according to JEDEC III. Comparisons with results for five other encapsulants considered in a previous study showed effects of complex interactions between encapsulant and flux.

All the seven encapsulants were then subjected to JEDEC I testing. Six of the seven encapsulant assemblies delaminated totally. The only encapsulant that did not totally delaminate was the Johnson and Mathey encapsulant.

Initial Results On The Encapsulation Of Dca Assemblies With Large Die And Very Low Stand-Off
Authors: Ravi Shankar Pitchika, Udayabhaskar V. Putcha and K. Srihari
Abstract: Preliminary studies were conducted in preparation of future efforts to underfill large die and/or die with fine pitches and thus very low standoffs. The risk of entrapping large voids under the die is seen to be very sensitive to materials selection and dispense temperature, whereas the dispense pattern seems to be less critical.

Comparative Reliability Testing Of Variable Frequency Microwave Curing Of Underfill Material To Convectional Oven Curing
Authors: Tien-Yi Liao, Daryl Santos and K. Srihari
Abstract: The curing of underfill encapsulant is often a bottleneck step in the manufacturing process of flip chip on board (FCOB) assemblies. A Variable Frequency Microwave (VFM), developed by Lambda Technologies, Inc., is investigated as a solution to significantly reduce the underfill curing cycle time. Most of the available literature have heralded the advances in microwave curing; but, only few raise the point about the quality of the curing. This work focuses on reliability testing of the VFM curing and compares the results to convectional oven curing. In this study, testboards with nine FCOB sites are used. Different combinations of flux and underfill are studied. JEDEC I and III conditioning are used and the primary metric of curing quality is determined by percent delamination after reliability testing. Reliability testing is primarily performed using various levels of Liquid-to-Liquid-Thermal-Shock (LLTS). General comparisons of performance of the two curing methods are provided in the report.

Finite Element Modeling Of Dca Assemblies: Underfill Delamination Trends
Authors: Yan Sha and K. Srihari
Abstract: Delamination of the underfill is usually a rate limiting step in thermal mismatch induced failure of DCA assemblies. Using the case of 25 mil thick die on 62 mil thick FR-4 boards as an example, this report explains experimentally observed trends on the basis of finite element analysis. In general, driving forces favor delamination from the chip passivation, starting either from the solder joints or from the chip corner. In the former case the delamination tends to progress inwards from the solder joints towards the chip center. In the latter case, the encapsulant delaminates inward along the passivation surface and/or upwards along the chip edge. Finally, there is also a strong driving force for cracking of the underfill itself to initiate from the chip corner and progress outward and downward at a 45o angle. Which phenomenon will dominate of course depends on the relative magnitudes of the driving forces, the local adhesion and the material cohesive strength. The present analysis suggests that good adhesion between underfill and solder joints might help compensate for the relatively poor adhesion endemic to epoxy-polyimide interfaces. It also suggests that voids in the underfill material may sometimes be detrimental.

Finite Element Modeling Of Dca Assemblies: Effects Of Die Thickness On Encapsulant Delamination
Authors: Yan Sha and K. Srihari
Abstract: The underfill delamination during thermal excursions is, among other, often sensitive to die and substrate thickness. Within the realistic die thickness range thinner die should generally lead to faster delamination. For a 10 mil thick die assembly failure would be dominated by delamination starting from the die corner. Like assembly warpage, the rate of this delamination is expected to vary with substrate thickness, peaking near a substrate thickness equal to that of the die. For a 20-25 mil thick die assembly failure is only sensitive to substrate thickness over a limited range. For sufficiently thin or thick substrates failure is dominated by underfill delamination starting around the solder joints. This phenomenon is not sensitive to substrate thickness.

Finite Element Modeling Of Dca Assemblies: Effects Of Heat Sinks On Encapsulant Delamination
Authors: Yan Sha and K. Srihari
Abstract: In the absence of defects at the solder mask surface, thermal excursions usually lead to encapsulant delamination originating at, and progressing along, chip edge or passivation. One preferred point of origin is around the solder joints, from which delamination tends to progress inwards away from the die edge first. This particular phenomenon is not very sensitive to parameters such as edge fillet quality, substrate rigidity, or the presence of a heat sink. For bare die on sufficiently rigid substrates good edge fillets exert a compressive stress on the encapsulant-passivation interface near the die corner, effectively suppressing delamination originating from there. However, for thinner substrates and/or in the presence of a heat sink on the back of the die this effect is reduced, allowing for a much faster delamination from the die corner.

The present work investigates the effects of attaching a heat sink to the back of the die. The sensitivities to parameters such as heat sink thickness and material, substrate rigidity, and the properties of the adhesive with which the heat sink was attached are assessed. Also, the effect of anchoring the heat sink to the surrounding substrate as well is evaluated. As far as encapsulant delamination is concerned, the preferred approach seems to be the use of an extremely compliant adhesive for heat sink attach.

“Finite Element Modeling Of Dca Assemblies: Effects Of Fr-4 Board Thickness, Modulus And Cte On Encapsulant Delamination”
Authors: Yan Sha and K. Srihari
Abstract: Thermal excursions, or specifically cooling, leads to the development of increasing stresses, and eventually encapsulant delamination, in DCA assemblies on typical FR-4 boards. These stresses, and their dependencies on board thickness, were assessed by Finite Element Modeling (FEM). The predicted trends were in good agreement with experimental observations of much faster delamination, starting from a different location, in assemblies on 18 mil than in those on 62 mil thick boards. The same modeling allowed the generalization of these trends, and the prediction of dependencies on board modulus and Coefficient of Thermal Expansion (CTE). No attempt was made to predict actual lifetimes.

Effects Of Ni/Au-Coated Substrate Pads On The Thermal Shock Resistance Of Dca Assemblies
Authors: Manish Ranjan and K. Srihari
Abstract: Effects of the substrate pad metallurgy on encapsulant delamination and electrical failure during Liquid-to-Liquid-Thermal-Shock were investigated. Two different sizes of die with full area arrays of solder joints were tested on 62 mil thick FR-4 boards with Cu/Ni/Au-pads. Effects of die spacing were considered as well. Results were compared to previous ones for perimeter array die, and for the same die on OSP-coated copper pads. There appears to be strong interactions between the effects of die size, die spacing, die layout and contact pad metallurgy.

Reliability Of Sgs Thomson Assemblies In Air To Air Thermal Cycling
Author: Daniel L. Blass
Abstract: This experiment examines the reliability of Direct Chip Attach (DCA) assemblies in Air to Air Thermal Cycling (AATC). DCA assemblies were built with a large SGS Thomson die (675 x 685 mils) on 62 mil FR-4 substrates. The die had an area array of 620 solder bumps and a polyimide passivation layer. The substrate pads were bumped with solder and coined prior to assembly. The standoff height was 4 mils. The material variables included encapsulant, flux, and substrate pad metallurgy.

Three encapsulants were investigated, Ablestik XP-032-395-6, Hysol FP4511, and Zymet X6-82-5T. Each encapsulant was used to underfill assemblies built with Kester 244 flux. Additionally, Hysol FP4511 was paired with an epoxy-based flux, Kester KK-4-21-4. The 62 mil FR-4 substrates had Cu/Ni/Au or Cu/OSP (Entek Plus) pad metallurgy.

The assemblies were subjected to 3000 cycles of AATC. The assemblies were examined with a Sonoscan C-mode Scanning Acoustic Microscope (C-SAM) for encapsulant delamination. For each combination of encapsulant and flux, assemblies with Cu/OSP substrate pads exhibited less delamination than with Cu/Ni/Au pads. Pad metallurgy had a stronger effect with the Kester 244 flux. Zymet had the least delamination but was plagued by die cracking. Ablestik-6 had delamination originating from the corner of the die, a problem that is suspected to be related to the encapsulant fillet. With Hysol FP4511, Kester 244 had more delamination than KK-4-21-4 on Cu/Ni/Au pads but less delamination on Cu/OSP.

Effects Of Solder Mask And Stand Off Height On Adhesion Of Encapsulant To Chip Passivation
Authors: Manish Ranjan and K. Srihari
Abstract: Flip chips with full area arrays of solder bumps were placed on 48-58 mil thick FR-4 substrates, underfilled with the FP4511 encapsulant from Hysol, and subjected to Liquid-to-Liquid-Thermal-Shock (LLTS). Testing was interrupted at intervals of 500 LLTS cycles and delamination of the encapsulant from the chip passivation measured. The type of solder mask on the substrate was found to have a strong effect on this, Probimer 52 leading to much faster delamination than Probimer 74. This dependence on solder mask type was stronger at lower standoff.

Evaluation Of Contact Pad And Solder Mask Registrations For The Csp/Dca Test Board-I
Authors: Parvez M.S. Patel, Suresh Jayaraman and K. Srihari
Abstract: The continued and ever increasing demand for high component and interconnection density, have necessitated the development of new technologies such as Chip Scale Packaging (CSP), Direct Chip Attachment (DCA) and micro Ball Grid arrays (m -BGA). This has lead to higher demands on the placement accuracy, due to tighter ball pitches and smaller land pads. It becomes necessary that the Printed Circuit Boards (PCB) used for such assemblies meet the requirements of electrical, dimensional, thermal and mechanical properties. Also in this environment of multiple vendor supplies, the properties across boards from each vendor have to be consistent and repeatable.

This report is an outcome of the evaluation to accomplish the above need to characterize the test vehicle CSPTB-1 supplied by different vendors. Particular attention is given to the assessment of pad sizes, masks registration, conductor width, solder mask undercuts and the various defects and nonconformities observed therein.

Measurements were performed to evaluate the following board parameters:

  • Vendor to vendor and board to board variation in the difference between the centers of the solder mask windows and the centers of the pads in terms of the misregistration.
  • The vendor to vendor and board to board variation in pad diameters.
  • The width of the solder masks openings at the DCA sites.
  • The areas of the exposed traces.
  • Variation in Undercuts for different mask types.

The results were compared to the design data to assess the deviation from the nominal values. The results of the evaluation can be summarized as under:

  • There exists a huge vendor-to-vendor variation in the pad diameters. The board-to-board and within board variations were vendor specific.
  • The mask misregistration was measured to be significant and was mask type and vendor specific.
  • Undercuts in solder mask were also mask and vendor specific.
  • DCA trench openings showed large vendor-to-vendor variations.
  • DCA sites showed a multitude of defects such as improper openings and debris in the trenches.

Direct Chip Attach Test Vehicle Design 1
Author: Anthony Primavera
Abstract: In an effort to focus on assembly of flip chip die onto low cost substrates, the first DCA Consortium test vehicle was designed and fabricated using conventional printed circuit board technology. Test vehicle 1, die were obtained from commercial vendors, Consortium Principal participation, and were fabricated by UIC staff in conjunction with the National Nano-Fabrication Facility at Cornell University. Die include perimeter array, staggered perimeter array, and non-uniform designs. Designs for the first test board included 1/4″, 1/2″, and 3/4″ die. Test chips for this board are the 8 mil pitch Delco die and a UIC designed 6 mil pitch staggered perimeter array. Test chip are a simple daisy chain stitched patterns to assess assembly parameters and board level reliability. Functional die applications included automotive, telephony, and consumer products will be assessed on other test board configurations. Several fully functional applications are being assembled and tested as part of the Consortium interaction with the Principal members. This document is a summary of test vehicle design 1 to be utilized in the project.

Overview Of The Csp/Dca Consortium Test Vehicles
Authors: Suresh Jayaraman and K. Srihari
Abstract: The demands in miniaturization and performance and rapid developments in silicon integration have placed immense pressure on chip packaging and board fabrication technologies. This growth in functionality and performance has resulted in the package shrinking to almost the size of the die in the Chip Scale Packages (CSPs). The flip chip eliminates the first level package altogether and offers greater savings in board real estate. The CSP/DCA consortium test boards 1, 2 and 3 were designed to help in the material selection, assembly process development and reliability evaluation of CSP and flip chip packages. This report provides an overview of the consortium test boards 1, 2 and 3.