1996 Reports

Downloads & Resources

Rework For Bga Components: The Component Replacement Process
Abstract: The component replacement process requires the precise placement of a new component on to the reworked site and the subsequent delivery of the required heat to reflow the solder to form a good solder joint. The quality of the solder joints that are formed is the most important factor that helps to ensure the reliability of the reworked assembly. Process related factors that could negatively impact the yield of the rework process and the reliability of the assembly should be considered. These factors include moisture related delamination, high die temperature related defects, soldering defects, secondary reflow of adjacent components, board warpage, etc.

The process knowledge gained from previous studies was used in this research to design and conduct experiments in replacing BGA components. Site redressing and flux compatibility related issues were considered. The replacement process parameters addressed in this research include the reflow profile, the use of flux, the reflow environment (air or nitrogen), and the methods used to deposit solder paste.

Rework For Bga Components
Abstract: This research focused on understanding the rework process as it applies to Ball Grid Array (BGA) components. Several rework process related research studies have been performed within the BGA/DCA consortium. These studies focused on the characterization of the rework system(s), the heating criteria adopted, the impact of moisture, the component removal process study, site redressing, the application of solder paste, and the component replacement process. Several important results were obtained and inferences were made from these studies, all of which are documented in several reports.

This report, however, provides a summary of the results obtained from the BGA rework related experiments that were performed within the BGA/DCA consortium. A systematic approach to temperature profiling that can be used for the development of the reflow profiles used in component removal and replacement is described. Process considerations and recommendations for each step of the BGA rework process are then presented.

Spreading Kinetics Of Eutectic Solder Paste With High Lead Solder Balls In Area Array Connections
Abstract: Two types of solder ball connections – collapsible and non-collapsible – are used in Ball Grid Array (BGA) and flip chip connections. The collapsible connections use an array of eutectic (or near eutectic) solder balls while the non-collapsible connections use an array of high lead solder balls on the component and eutectic solder on the corresponding substrate pads. In order to develop a robust assembly process for such devices, it is necessary to have a proper understanding of the factors that affect the reliability of these solder joint connections.

A major concern in non-collapsible connections from the metallurgical perspective is the inter-diffusion that occurs between the eutectic solder and the high lead solder ball (on the component) during eutectic reflow. The rate of diffusion varies and depends on reflow temperature, the dwell time at the reflow temperature and the number of reflow cycles or rework operations. But, inter-diffusion raises the minimum Pb-concentration, and thus raises the melting point, which may affect subsequent rework. Also, the inter-diffusion may eventually affect the reliability of the solder joint. This report discusses the kinetics involved in the diffusion of eutectic solder with high lead solder ball.

Torsional Testing As A Comparative Tool For Reworked Versus Non-Reworked Pcb Assembly
Abstract: Printed Circuit Board (PCB) assemblies with surface-soldered components are often subjected to torsional flexing to ensure their structural integrity (Engel, 1990). The present work examines reworked versus non-reworked components exposed to torsional loading. A torsional testing device which imposed cyclical mechanical loading on single-component square PCB coupons was created. The amplitude (angle) and frequency (rate) of twist was constant throughout the testing. The goal was to compare cycles-to-failure for non-reworked components to those that had undergone rework to ensure that the reliability of the reworked component is at least as good as the non-reworked component. In addition, the reliability of assemblies reworked using solder paste and flux were compared. In each case, the success of the rework process could be inferred from the cycles-to-failure data.

Rework System Characterization And Heating Criteria Evaluation
Abstract: This research evaluated three different systems that could be used for BGA rework. The heating method used by these rework systems was studied. Modifications were made to the rework system provided by Micro Electronic Systems (MES). The nozzles available with the initial MES rework system were modified. Several modified nozzles were designed and evaluated. Finally, an acceptable nozzle design was identified. The results obtained at each stage of the equipment evaluation process are provided in this report. A study was also performed to understand, through experimental methods, the significance of the criteria that are commonly used to evaluate rework systems from a heating perspective. These criteria include the thermal gradient, die temperature and the temperature measured at locations on the board adjacent to the reworked component. Several conclusions were drawn based on this experimental research effort.

Rework For Bga Components – The Component Removal Process
Abstract: This research focused on understanding the rework process as it applies to Ball Grid Array (BGA) components. The component removal segment of a rework process should non-destructively remove the defective component from the board without causing any damage to the Printed Circuit Board (PCB) assembly including the substrate and the other components. Therefore, the objective of this component removal study was to design and develop a reliable component removal process which would non-destructively remove the component while concurrently minimizing damage to the rest of the PCB assembly. The component removal related process parameters that needed to be identified included the reflow profile, the use of flux, the environment used during reflow (air or nitrogen), etc.

An overview of the rework station that was used for component removal is presented. The experiments that were performed in this study are described. Information on the material used, the experimental procedures adopted, the development of the reflow profiles and the results of the experiments are documented. Important process related observations are presented.

Shadow Moire Analysis Of Bga Components
Abstract: A Ball Grid Array (BGA) package is made up of layers of different materials on either side of the silicon die. The thermal mismatch between these layers leads to an out-of-plane displacement (warpage) of a BGA package, when subjected to a change in temperature. The amount of warpage is one critical factor that may influence the assembly yield and reliability of the component. Severe warpage could cause cracking of the silicon die and large plastic deformation of the solder joints. More importantly, however, warpage during reflow, concurrent with other factors such as solder joint volume variations, may lead to opens or shorts in the assembly. Most direct techniques only measure warpage at room temperature and incomplete knowledge of the properties involved complicates the prediction of temperature dependencies. The shadow moiré technique is an unique tool that can be used to determine the out of plane displacement of a component as a function of temperature.

This report provides a brief description of the Shadow Moiré technique. The technique was used to study twelve different BGA packages, providing data on the relative change in warpage with temperature. A Cyber Optics laser profilometer was used to measure absolute warpage at room temperature. This was used as the basis for determining the warpage at reflow temperatures.

Warpage Of Bga Components And Assemblies
Abstract: A BGA package is composed of layers of material with different thermal and physical properties. The thermal mismatch between the various layers of the stack leads to out-of-plane displacement (or warpage) of the package during thermal excursions. It is well known that such warpage occurs in a BGA package, but in most cases it is unavoidable. A severe warpage can prove to be fatal to the yield and reliability of the assembly.

This report covers an initial study that was performed to characterize and understand the warpage in BGA components during manufacture and assembly. A brief note on the occurrence of warpage during rework of the BGA components is also provided.

Post Reflow Inspection Techniques And Equipment For Area Array Devices
Abstract: Surface Mount Technology (or SMT) is increasingly displacing Pin-Through-Hole (or PTH) technology as the technique used to mount Integrated Circuits (or ICs) on Printed Circuit Boards (or PCBs). A major reason for this phenomenon has been the need to keep pace with the increasing demands for enhanced component density and functionality of the Printed Wiring Board (or PWB) assemblies. Area array packaging Ball Grid Array (BGA) and Direct Chip Attach (DCA) of the surface mount devices in particular, can help provide larger Input/Outputs (I/Os) with a smaller component footprint.

Post reflow inspection of the area array devices is becoming extremely challenging since the majority of BGA and DCA joints are completely hidden from view, and even the peripheral joints are difficult to examine due to the low standoff of the BGA/DCA and the surrounding SMT components. Therefore, any inspection technique used to evaluate the quality of the reflowed joints must be capable of imaging through the overlaying material, the silicon and the metalization layers of BGA and DCAs. Techniques used to inspect area array components after reflow commonly use one of the several types of radiation.

Inspection techniques that are currently used are Acoustic Micro Imagery (AMI), X-ray laminography, X-ray tomosynthesis, and visual inspection. Visual inspection has very limited application due to its inherent nature of not being able to penetrate silicon surfaces. Thermal Imaging technique is in the stage of research and is considered to be a potential inspection technique for post reflow inspection of area array packages. The Magnetic Resonance Imaging (MRI) technique too has a great scope for application for inspection of array packages but for its cost. A compilation of the companies which manufacture equipment for post reflow inspection of BGAs and DCAs, cost of the equipment and the salient features of the equipment are also provided.

The Self Centering And Package Weight Experiment
Abstract: One of the advantages of surface mount PCB assembly using area array devices is that the packages tend to self align during reflow. This phenomenon can compensate for a great deal of component misregistration that can result from the component placement process or from subsequent handling. The mechanism by which an area array package attains self centering is indeed complicated. This study did not address every facet of the phenomenon. However, by using an experimental approach, this study attempted to identify the maximum range of misalignment that can be compensated by the packages self centering capability for a given set of process parameters. Also, the impact of package weight on the solder joint standoff when the assembly is subject to multiple reflow passes was studied.

The Bga Assembly Experiments
Abstract: When compared to high pin count ultra fine pitch leaded surface mount packages, the Ball Grid Array (BGA) type packages provide several benefits including a smaller package size, better thermal and electrical performance, and the utilization of existing surface mount equipment and processes. Besides, due to the potential for high assembly yield, there is a great deal of interest in the BGA type package within the electronics industry. While high assembly yields have been reported, the details of the process knowledge needed to ensure these yields is not widespread.

The focus of this study was to understand the assembly process, including the necessary parameters and the related limitations, needed to ensure high yields when populating BGA type packages on printed circuit boards.

Four test vehicles with different board designs were built to provide an initial understanding of the surface mount PCB assembly process when BGAs were used. Test vehicle 1 was designed to evaluate the impact of the board thickness and the solder bump coplanarity on assembly yield. Test vehicle 2 helped to study the intricacies of the assembly process when QFPs and BGAs were used on a board. Test vehicle 3 was designed for reliability testing. This test vehicle was also used in the design of experiments build. Test vehicle 4 was used for reliability testing as well as for the power cycling tests.

Process Recommendations For Bga Assembly
Abstract: Recommendations are presented for a BGA assembly process. When the recommended process was used, zero process defect was achieved out of more than one million joints. A nominal defect level of 0.05 ppm was estimated at a 95 percent level of confidence. Defective packages with missing solder bumps significantly impacted yield. Process windows are described for assembly processes such as stencil printing, component placement and reflow soldering. Recommendations on other process and material related issues including the solder paste used, stencil design, pad design, and the components used are also presented.

Bgas And Peripheral Leaded Devices – A Cost Comparison
Abstract: The last decade has seen an increasing demand for smaller and more densely populated printed circuit boards. This is partly due to the market driven need within the electronics industry to reduce the size of products while concurrently enhancing their capabilities. Consequently, electronics packaging industries are turning towards component packages like ball grid arrays as replacements for the traditional peripheral leaded devices. Ball grid arrays offer cost savings in terms of reduced board real estate, increased yields, better electrical performance, better assembly yields and reduced design to production cycle time. However, these cost benefits need to be quantified in order to justify the use of these devices.

A software based cost model has been developed to estimate the cost of assembling a board with peripheral leaded devices like a QFP or a TAB component and to compare this cost with the assembly cost of a functionally equivalent ball grid array. This cost comparison is performed without changing the functionality of the board. The values of the cost factors considered are user defined. The software model also allows the user to save and retrieve the input and output values of a previous cost analysis. This feature allows the user to perform what if analysis. The metric used for comparison is the cost of assembly per board. It has been computed by considering cost factors like the equipment cost, labor cost, material cost, rework cost, etc. This cost model has been developed using Microsoft EXCEL software (Version 4.0).

Characterization Of The Placement Machine
Abstract: The component placement machine is the perhaps most complicated piece of equipment in a surface mount printed circuit board assembly line. The component placement machine needs to accurately locate and place components at their designated locations on the board. Components may not always be accurately located at their nominal locations due to sources of deviation such as the substrate, the component and the placement machine. Less than perfect placement could induce a reduction in yield. This report describes the technique used to characterize the surface mount placement machine used in this study. A precision plate was used along with precision components in a systematic manner to evaluate x, y and theta related accuracy. It was determined that the placement machine under review was more than capable of placing standard ball grid array components in an accurate and repeatable manner.

Solder Paste Testing And Evaluation
Abstract: This research focused on the testing and evaluation of the various solder pastes with respect to their use in BGA assembly. An auxiliary output of this research was the identification of the special characteristics that a solder paste should have for successful use in the BGA assembly process. The testing and evaluation was done on twelve no-clean solder pastes. The matrix of solder pastes are representative of pastes that contain fluxes with different solids content, pastes that can run in air, nitrogen or air/nitrogen atmospheres, pastes that are either resin or rosin based, etc. The selection of the specific pastes was also based on prior experience and the extensive testing that had been done over the years at the Surface Mount Laboratory at Universal Instruments Corporation. With the exception of the SIR and the ECM tests, all other tests were done at the Surface Mount Laboratory. The SIR & the ECM test were done at Trace Laboratories, Chicago, Illinois.

The solder pastes that were tested were eventually classified as either acceptable and non-acceptable pastes. Six pastes (out of the twelve) proved to be acceptable while the rest were non-acceptable due to one or more characteristics. The pastes that are classified as acceptable passed all the tests. This report contains the testing and evaluation procedures used, the data and the results obtained for each paste for all the tests conducted, and the inferences made.

An Introduction To Rework For Area Array Components
Abstract: Area array packages are being increasingly used in the surface mount Printed Wiring Board (or PWB) assembly domain. These packages are gaining acceptance within the electronics industry due to their unique characteristics and high process yields. The rework of area array components is a significant challenge, especially with double-sided PWB assemblies. The purpose of rework is to remove and replace a component non-destructively without affecting the performance and reliability of the PWB assembly.

This report provides an overview of the rework process for BGA components. A survey of the relevant literature is provided along. The domain related factors that need to be considered are discussed. A review of existing rework systems is also provided.

Bga Failure Analysis
Abstract: It has been acknowledged that the reliability of Ball Grid Array (BGA) packages is perhaps one of the more important factors that would determine its widespread use. This report describes the analysis of failures seen in a variety of BGA packages. The packages studied have various solder bump configurations including full array, perimeter arrays, different die sizes, different pad coatings, and different structures (Cavity up design Versus Cavity down structure). Also, components were subjected to one of two thermal cycles which were -40° to 125°C and 0° to 100°C respectively.

The objective of this research was two-fold. First, the behavior of these components was studied under the specified test conditions. Second, a methodology that could be used for conducting failure analysis was developed. The failure modes studied are (I) thermal fatigue (failure within bulk solder) and (ii) fracture at the interface between the solder joint/ component and the solder joint/board. After thermal cycling, the test assemblies were subjected to electrical testing and X-ray analysis. The first and the last failures observed for each of the two temperature cycles for each component type were cross sectioned to analyze the failure mode. The dye penetrant test was then used to detect the location of the failed joints in the remaining components.

Several conclusions were drawn from this failure analysis study. A greater number of components and joints (per component) failed in the -40° to 125°C cycle as compared to the 0° to 100°C cycle. In most cases, the failure mechanism observed in the -40°~125°C temperature cycle was delamination. The full array devices showed pin failures just below the edge of the die whereas the perimeter array devices showed pin failures along the outer perimeter. No failure was observed at the board side alone. In the few cases, when a failure occurred at the board side, there was a crack at the component side as well. In general, more joints per component failed on HASL pads in the -40° to 125°C cycle as compared to the components on OSP pads.

Ball Grid Arrays (Bgas) – A Review
Abstract: Market driven demand for smaller and lower cost consumer electronic products with enhanced functionality has resulted in an urgent need for semiconductor packaging technologies which can accommodate larger, more complex integrated circuits in smaller and thinner packages. Although the use of fine pitch technology in Printed Circuit Board (PCB) assembly has increased substantially, the electronics industry hesitates to enter the ultrafine pitch arena due to the possibility of decreased process yields.

Ball Grid Arrays (BGAs) are the result of a new packaging technique which by all indications has a promising future due to its leadless package configuration and its compatibility with the existing standard surface mount PCB environment. With larger pitches and ball sizes, BGAs eliminate a significant amount of the assembly problems encountered in fine pitch PCB assembly. However, the use of BGAs is not widespread since it is a new technology that is not sufficiently supported by adequate infrastructure and reliability data. Consequently, the use of BGAs is not as popular as it should be. However, indications are that the use of BGAs will increase in the near future.

This report surveys the BGA domain. BGA technology is introduced and related publications are reviewed. Topics addressed include the types of BGA packages, current status of BGA use, and BGA standards. Process research in the BGA domain is studied, and ideas for future research are presented.

Effect Of Solder Joint Geometry On Predicted Fatigue Life Of Ball Grid Array Packages
Abstract: This report addresses issues related to the computational modeling of ball grid array joints. Both solder joint shape prediction and thermal fatigue life issues are presented. The objective is to explore the design space of the solder volume and standoff height consistent with that of a typical ball grid array package used commercially. To this end, typical solder volumes, pad diameters, and standoff heights for a plastic 225 BGA package were supplied by the Universal Instruments Corporation. They were used in the determination of the effect on solder joint fatigue life as the solder volume was changed with other geometrical parameters (pad diameters, standoff height) remaining constant. Other variations included holding the volume fixed and increasing the standoff height (the reverse of the above situation) and increasing both standoff height and volume but retaining the same general shape of the joint (the easiest case being that of a cylindrical joint). A case involving a single joint with a different solder volume from all other joints in a package is discussed. Lastly, the use of the integrated matrix creep method is discussed with reference to alternative averaging methods.

Ball Grid Array Technology Complete Overview
Abstract: In an attempt to understand the major assembly and long term reliability aspects of current ball grid array devices, the Universal Instruments Ball Grid Array Consortium was established. Major research focused on materials and construction of ball grid array devices, assembly to organic printed circuit board material, second level attachment solder joint reliability, rework, and in some cases first level package integrity. Primarily, organic based ball grid arrays were incorporated in the evaluation, although a few other technologies were investigated including ceramic and micro ball grid arrays. Process and long term reliability were the main intended areas of study, however, discovery of many material and package construction related issues and problems were identified during the course of the evaluation. In turn, a major emphasis was placed on identification of underlying problems and causality of discovered issues. This document should serve as a general guide to the realm of organic ball grid arrays. This document, (Primavera, Anthony – 1996 – BGA Technology A Complete Overview), is a companion to all other documents focusing on individual topics of interest. An executive summary has been prepared to give a concise synopsis of the discoveries found in the BGA Consortium. The executive summary is found in (Westby, George, 1996 – BGA Executive Summary).

Solder Mask Attributes And Chemistries
Abstract: There is literally a myriad of combinations of chemical materials currently being used in solder mask formulations. It is generally correct to say that the photosensitive solder masks, whether dry films or liquids, are based on photo-cross linked acrylics, photo-cured epoxies, acrylate epoxies, photosensitive isocyanates, and/or any combination of these materials. Clearly this expansive statement cannot hope to detail the actual chemistry with any specific details of the chemical nature. It must be noted that SM must withstand a variety of cleaners, fluxes, paste vehicles, and soldering conditions. Equally, since the SM is an integral part of the final assembled PWB, it must pass all thermal environmental tests of the PWB. However, several generalizations can be made.

Ball Grid Array Assembly: Ibm – Austin Texas
Abstract: Currently, IBM Austin Texas is providing printed circuit boards (PCB) boards and assembly for IBM internal products including RISC, portable products, and workstation applications. Many products utilize ceramic ball grid array (BGA) and column grid array (CGA) components. With tape carrier array and plastic BGA packaging well underway at IBM and industry wide, an adequate assembly process is being developed for future IBM internal products. A first pass assembly and repair process has been developed for plastic BGA components at IBM Austin, in conjunction with the Universal Instruments BGA Consortium. This documentation presents highlights and overview of the process as currently developed. This work has been accomplished at the IBM Austin Texas facility under direction of Mr. Leo Anderson. The project originated from a joint effort between IBM and LSI Logic Corporation and has been extended to be included in the Consortium activities as per the request of LSI Logic. Work focused on assembly and repair of double sided PCBs populated with daisy chained 225 pin plastic BGA components from LSI Logic, manufactured by Citizen in Japan. The PCBs were manufactured by IBM Austin Texas PCB division.

Mds Testing Of Ball Grid Array Assemblies
Abstract: Currently, IBM Microelectronics – Endicott New York, is providing printed circuit board (PCB) reliability mechanical deflection testing (MDS) analysis of IBM internal products including RISC, portable products, workstation motherboards and other applications. As part of the investigation into mechanical reliability analysis of ball grid array (BGA) assemblies, in conjunction with the Universal Instruments BGA Consortium, MDS testing was performed on 225 pin plastic BGA assemblies. This documentation presents highlights and overview of the MDS testing process as currently developed. This work has been accomplished at the IBM Microelectronics – Endicott, New York facility under direction of Mr. Aleksander Zubelewicz. Work focused on MDS testing of PCBs populated with daisy chained 225 pin plastic BGA components from LSI Logic, manufactured by Citizen in Japan. The PCBs were manufactured by IBM Austin Texas PCB division. PCB assembly was performed at Universal Instruments Corporation.

Bga Power Cycle And Vibration Testing
Abstract: In an attempt to understand the long term reliability aspects of current ball grid array devices, the Universal Instruments Ball Grid Array Consortium established several testing criteria for use in determining first level and second level reliability of BGA assemblies. Major research focused on integrity of materials of ball grid array devices, long term solder joint reliability. Primarily, organic based devices were incorporated in the evaluation, although a few other technologies were investigated including ceramic and micro ball grid arrays. As a participant in the BGA Consortium, Trace Laboratories provided testing services including, materials, power cycle testing, vibration testing, and accelerated thermal cycling. This document is a summary of the power cycle test results, vibration testing, and overview of the accelerated thermal tests performed. Original documentation, test data, and other recorded information is retained by the Consortium and is available for review.

Out-Of-Plane Solder Joint Defect Prediction
Abstract: The combined effects of component and board warpage during reflow, together with solder volume and pad size variations, may lead to opens, satellite formation, or bridging in BGA assembly. In DCA assembly some of these variations are, of course, negligible but because of the smaller tolerances the remaining effects are still critical. A Monte Carlo based computer program has been developed to predict assembly yields on the basis of statistical variations in the various parameters.

Wettability Test/Coatings: Osp Vs Hasl
Abstract: Traditionally, component pads on Printed Circuit Boards have received a Hot Air Solder Level (HASL) finish which serves as a protectant to the underlying pads. However, due to the increased packaging density of assemblies and the shortcomings of HASL finishes, there is a move to use alternate surface finishes such as Organic Solder Protectants (OSP) To establish the commercial use of OSPs, a thorough study of the solderability of OSP coated pads over multiple reflow cycles needs to be performed.

The solderability of two commercial OSPs and one HASL coating on copper was evaluated and compared. The solderability evaluation procedure used was the wetting balance analysis. Four fluxes were used in conjunction with each of the protective coatings over multiple reflow passes. Both ambient atmosphere and a nitrogen atmosphere were used in the wetting balance equipment. Coated copper wire samples were prepared (for the required number of reflow cycles) through a Soltec oven with an ambient atmosphere. The measurements of wetting force and wetting time were recorded using the Kester KWB-1000 wetting balance tester.

Organic Surface Preservatives (Osps)
Abstract: OSPS are organic surface preservatives that protect copper surfaces from oxidizing. These protective coatings have been described as anti-tarnish materials and have been used by manufacturers of printed-circuit-boards for a number of years. Organic anti-tarnish coatings provide a thin coverage over copper and range in thickness from a few hundred angstroms to several thousand angstroms. Current industry practice has been to protect the copper surface of a PWB with HASL.

The OSPS coatings are an organic based material and are defined as nitrogen heterocycles which defines suitable azole chemistry. The chemical ingredient in the coatings react only to copper and copper alloys to form a thin coating which prevents moisture and air from coming in contact with the copper surface thus preserving solderability during storage.

Researchers at AT&T Bell Laboratories have separated OSP coating materials into three types.

  • Azoles applied as monolayer films, 30-50 angstroms films
  • Modified azoles applied much thicker, 1000-5000 angstrom films
  • Prefluxes which range 3000 to 6000 angstrom films

The drive for OSPs has been driven by emerging packaging technology. The requirements for OSPS are good solderability, planar surface-mount pad topography, environmentally friendly and low PCB warpage and distortion.

The literature1, 2, 3, 4, 5, 6, 7, 8 and 9 reports the use of azole chemistry such as imidazole, benzimidazole, and benzotriazole to prevent the tarnish of copper printed wiring boards.

Laminates And Solder Mask Used In Pwb Applications
Abstract: The Printed Wiring Board (PWB) forms the primary structure on which electronic components are mounted and soldered in position. For rigid PWB applications, fiber-reinforced resin dielectric materials clad with copper sheets (referred to as laminates) are most commonly used. As the expectation in robustness in the circuit cards and boards keeps increasing the properties of laminates and its constituents requires greater attention. The laminate consists of three main constituents, namely the fabric, the resin and the metal foil. The properties of all these components determine the suitability of the laminate for the different PWB applications. This report delineates the procedure for manufacturing the laminates and its various constituents. The IPC test procedures used to determine the properties of these laminates are discussed. A brief note is included in this report on the electrical, thermal and mechanical properties of the laminates. A listing of the various manufacturers of the laminates and its constituents along with the properties of their products is also provided. A brief note on solder mask requirements for area array application is also provided.

Rework For Bga Components: Moisture Sensitivity Study
Abstract: Plastic Ball Grid Arrays (PBGAs) are sensitive to moisture induced delamination and popcorning during solder reflow. In general, the development of assembly processes therefore needs to include studies on the floor life of the individual component types under typical factory conditions. Whereas one may never need to consider components that have been completely saturated with moisture for the original assembly, however, such components may be returned for rework as part of field failures. If such components are to be removed for reuse or failure analysis without further damaging them, these may therefore have somewhat stronger bake out requirements.

In the present study, moisture absorption trends were studied for ten different BGA types. Motorola 225 PBGAs were then selected for an in-depth case study. Effects of multiple absorption and bake out cycles and different humidity levels on absorption kinetics were investigated. The effect of bake out temperature on desorption was measured. Effects of reflow profile parameters on delamination resistance were determined, and the required bake out time after moisture saturation identified.

Theoretical considerations showed moisture absorption and desorption to be multilayer diffusion processes. Theoretical predictions of delamination would require, at least, modeling of moisture concentration distributions versus time. However, since the material properties, notably the diffusion coefficients, of the individual layers are generally not well known, the floor life and minimum bake out time for a given component cannot be predicted theoretically. In fact, we cannot even scale between different levels of humidity. Extensive experimentation is therefore always needed.

Bga Solder Ball Volume Variation Study
Abstract: One significant component related issue is the effect of solder volume variation on solder joint shape, assembly yields and reliability of BGA solder joints. The dominating portion of the BGA joint is the preformed solder sphere. It is important to define levels of variation among solder preforms, used for BGA applications, in order to properly define volume variation within the BGA joint. This has been done for 10 different lots of solder spheres from various manufacturers. In conjunction with this, it is also critical to define current levels of volume variation that exist on BGA packages from each vendor. Solder ball and joint volume, for these two experiments, is approximated by accurate and repeatable measurements of diameter. The metrology is performed using a View Precis 3000 coordinate measuring machine (CMM) and various fixture supports for both the solder preforms and BGAs. These tools allow us to obtain accurate and repeatable measurements of solder ball diameter in both preformed spherical shape and truncated sphere shape. The data generated from metrology of unattached spheres and BGAs is compared for correlation. The characterization of package volume variation is used for understanding assembly yields and long term package reliability. Models of solder joint volume are developed from measured data and used as input for finite element reliability testing. Estimated mechanical fatigue lives are referenced for a series of BGA solder joint volumes having fixed pad and standoff dimensions. Refer to (Holub, Ira & Pitarresi, James – 1995 Effect of Solder Joint Geometry On Predicted Fatigue Life Of Ball Grid Array Packages), Universal Consortium. For information on assembly related effects, refer to (Huang, Yu-Wen 1996 – BGA Assembly Experiments), Universal Consortium. The BGA metrology results were also inspected for diameter dependence or bias within the package array. This is performed by using box plots to display diameter as functions of array row and column.

Bga Missing Solder Ball Issue
Abstract: One of the most important issues identified for the Ball Grid Array evaluation is missing solder balls. This issue questions current and future means of inspection as well as current methods of manufacturing. During our inspection we identified 360 missing solder balls across various packages. The projected assembly yields would exceed 100 ppm if these defective devices were not identified and rejected during component inspection. The total number of solder joints assembled by the consortium is approximately 2,120,115. Based on this and the total number of missing solder balls identified: At a 95% Confidence level, expected yields from missing ball defects would correspond to 152 ppm(-3 sigma), 170 ppm(mean), and 187 ppm(+3 sigma).

The majority of the missing solder balls detached at the solder-nickel interface. This implies there is a problem within the plating or attachment stages of production. In order to properly characterize this issue, shear strength tests were performed on packages from each vendor. From these tests, we can study the load versus displacement plots and failure mechanisms, for each solder ball shear test, and compare results between packages. The shear tests were carried out on an INSTRON materials testing machine. This issue has been thoroughly investigated in the following report.

Bga Metallurgical Evaluation
Abstract: An important component issue is the metallurgicall characterization of the BGA interconnects and solder joint attributes for each package type. Certain packages utilize specific solder alloys. For example, most ceramic ball grid arrays (CBGA) and tape ball grid arrays (TBGA) employ a ‘high lead’ solder, usually 10Sn/90Pb or 5Sn/95Pb for increased solder joint height. Plastic ball grid arrays (PBGA) use eutectic solders, commonly 63Sn/37Pb/2Ag. Different solder alloys bring different material properties to the final solder joint. Solder melting point and intermetallic qualities, for example, affect the solder joint stiffness, reliability, and assembly yield.

Included is a metallurgical characterization of ten solder preform samples, of various diameter and alloy, and of the solder interconnects and joint attributes for different BGAs. Cross sectioning, in conjunction with the use of optical microscopes and metallagraphs were tools used in this investigation. Scanning electron microscopy (SEM) using Energy Dispersive X-ray (EDX) was also used to evaluate the solder specimens. Differential Scanning Calorimetry (DSC) was used to study the melting point of various solder alloys.

Bga Printability Study
Abstract: The screen print process is empirically modeled for the selected BGA components in this study. Two important print process variables, squeegee pressure and print speed, are evaluated for circular device openings whose diameters are between 14 and 40 mils. A single step stencil in 6 mil thickness is selected. The objective of this research is to evaluate the effects of the print process variables over the responses. Two responses related to the solder paste deposition are evaluated. These are measured volume, and average height. A laser based inspection system, SVS 7530, is used to measure the solder paste deposition on a bare board. The results are analyzed by multiple linear regression technique. Response surface methodology is used to obtain empirical models of the process. The following sections outline the research content, solution methodology, and the results obtained.

Voids In Solder Joints Of Area Array Assemblies
Abstract: The electronics industry is witnessing a continuous trend toward miniaturization and the integration of multiple functions in electronic products. This is necessary to meet market driven demands such as higher functionality and the concurrent miniaturization of electronic products at the same or even lower costs. Voiding in the solder joints between the printed circuit board and the surface mount components is a solder defect which causes concerns in surface mount assemblies. Voids occur usually as spherical shaped cavities inside the solidified solder material. Solder joint integrity is very important to guarantee the faultless performance and the long term reliability of electronic assemblies, especially those that contain fine pitch and/or high input/output components. The occurrence of voids in solder joints needs to be minimized. This research focuses on ball grid arrays which typically have a large number of inputs/outputs.

Several theories that attempt to explain the causes for void formation can be found in the literature. The experimentation that has been carried out has often resulted in inconsistent results, and in controversial explanations for the occurrence of voiding. A systematic experimental approach has been used in this research to address the causes for void formation in BGA assemblies. The majority of these experiments were undertaken with eutectic solder pastes that were obtained from different paste manufacturers. The solder paste was stencil printed onto BGA test boards. Glass slides were used to cover the solder paste deposits and to simulate the sandwich construction of a BGA solder joint. The reflow soldering process was accomplished through the use of a forced convection oven. Subsequently, the solder joints of the test samples were examined for voiding by a transmission X-ray inspection system. In order to evaluate voiding in solder joints, the number of voids along with their diameters was determined from a gray scale pixel image generated by the X-ray machine. The impact of several process related factors were considered in these experiments.

The observations and inferences made from this research work have shown that the void formation process is affected by reflow profile parameters such as soak time, soak temperature, and peak temperature. The adjustment of these reflow parameters in order to minimize voiding was found to be paste dependent. One of the solder pastes that was used revealed no significant influence of these reflow parameters (soak time, soak temperature, and peak temperature) within the range that was investigated. Lower void contents were measured when the reflow process was performed with a large soak time, a short dwell time, and under a nitrogen atmosphere. Voiding increased when the printed solder paste deposits were exposed for longer times to ambient air prior to the reflow process. The void content was also enhanced when the applied solder paste volume was augmented. The cleanliness of the pad surface and the composition of the pad coating were also found to be important factors which affect the number of voids in the solder joint.

Bga Inspection: X-Ray Laminography
Abstract: Ball Grid Array (BGA) technology is being increasingly used in industry today. However, inspecting and verifying the integrity of the solder joints of a BGA component poses considerable problems since all the joints are on the underside of the component. Consequently, they cannot be visually inspected. Another concern in BGA technology is the inspection of the solder joint after rework (Lau).

Through-transmission X-ray imaging is a feasible technique that can be used for solder joint inspection of BGAs. However, this technique has some limitations especially in non-collapsible BGAs. This is because through-transmission imaging is prevented by the overshadowing effect of the high lead ball on the eutectic solder. Cross-sectional X-ray laminography is a technique which can overcome this limitation.

The suitability of the laminographic inspection technique in identifying the defective BGA solder joints is discussed in this report. A board populated with Plastic Ball Grid Array (PBGA) and Tape Ball Grid Array (TBGA) components was considered in this case study. The test board used (provided by one of the consortium members) was subjected to a particular rework process.

While the test board was populated with several 225 ball PBGAs from LSI Logic and 432 ball TBGAs from IBM, only two components of each type were subjected to X-ray laminography (at Four Pi Systems). The components that were studied had been previously reworked. This research study correlates the data obtained through X-ray laminography to the solder joint defects observed in these components. The defective solder joints that were identified using the laminography data were verified by physically cross-sectioning the components at the specific locations.

X-Ray Laminographic Analysis Of Bga Test Vehicles
Abstract: Ball Grid Array (BGA) components are being increasingly used in high volume production. This is especially true in applications where high I/Os are needed and space is a constraint. However, the process used to assemble BGA components on the printed circuit board assembly poses certain challenges to the manufacturing engineer when viewed from an inspection perspective. Inspection of BGAs is difficult to achieve because the physical attributes of the BGA package make it very difficult to inspect the solder joints. Only the joints which are on the periphery of the component can be inspected visually. However, this process is difficult and time consuming. Hence, techniques such as X-ray laminography have been adopted for solder joint inspection.

As a part of the research performed within the BGA consortium, some ‘BGA test vehicle’ assemblies were subjected to X-ray laminography analysis (at EMPF). This report aims at the detection of solder joint defects through the use of statistical data obtained from X-ray laminographic analysis. Also, the solder joint measurements obtained through X-ray laminography are correlated with the potential solder joint failures such as opens, shorts, delamination and warpage that have been identified in the same BGA assemblies. Most of the questionable and abnormal solder joints, which are likely to cause failures later during their operating cycles, have been identified through this study.

Power Cycle Simulation Of Bga Components
Abstract: A simulated electrical power cycle was studied for two plastic BGA package families; the 256 perimeter BGA package and the 204 Super BGA. The objective was to study the thermally induced deformation in the solder joints so that the fatigue life could be computed. A thirty minute cycle was used, simulating power on for fifteen minutes followed by power off for fifteen minutes. The power dissipation used in this study was assumed to be 2W. The Crack Growth Rate Model, developed at Motorola, was used to predict the characteristic and component N50. The procedure used to determine the predicted component fatigue life was to first perform a transient thermal cycle simulation with a power input to the die of 2W. The nodal temperatures resulting from this simulation were used as the input temperatures into a structural model to determine the fatigue life of the solder joints. The 256 BGA reached a steady-state temperature in approximately two and one-half minutes with the maximum temperature at the die edge of 116°C and 55.7°C at the inner solder joint. The 204 Super BGA also reached steady-state temperature in approximately two and one-half minutes with maximum die edge and inner solder joint temperatures of 83.6°C and 67.2°C, respectively. Upon doing the fatigue analysis of the two packages using the Crack Growth Model, the N50 for the 256 BGA component was 57,400 cycles and for the 204 Super BGA it was 27,000 cycles.

Finite Element Modeling Issues For Bga Components
Abstract: The damaging effects of imposed in-plane, out-of-plane, and combined in and out-of-plane displacements on three different solder joint configurations was examined. Three solder joint attachment details were studied: 1) mask defined at the component and Printed Circuit Board (PCB), 2) mask defined at the component and pad defined at the PCB, and 3) pad defined at the component and PCB. Each configuration was subjected to the twenty minute 0°C to +100°C thermal cycle adopted by the Consortium. Finite element models of the three configurations were built and the integrated matrix creep method was used to predict the fatigue lives of the solder joints. The results from the models showed that out-of-plane displacements cause significantly more damage to the joint than equivalent in-plane displacements. As expected, the combined in and out-of-plane displacement caused the most damage. However, the combined loading did not obey a linear damage rule.

Bga Assembly And Reliability Analysis
Abstract: This report covers the empirical modeling and analysis aspect of the BGA assembly yield and reliability failure analysis. The effects of various input variables are evaluated on the measured response variables. The main objective is to understand complex relationships between the input and output variables. The modeling aspect of this study is empirical and purely data driven. The output (response) variables are the defects encountered in the BGA assemblies. The defects are the bridged or open joints which are mathematically represented with 0 (no defect) or 1(defect). Two thermal test cycles, and two pad metallurgies (copper versus HASL), are used in a 64 board experiment. In this study, the important input variables are considered and measured at the different stages of the assembly process. Solder paste deposition related variables are volume, average height, and area of each joints measured by an SVS 7530 laser inspection system. The ball diameters on the devices and pad diameters on the boards are measured by a View Precis 3000, automated vision metrology system. This machine is also used to examine the joints after the reflow process. The opened and bridged joints are pointed out and cross sectioned. The circularity of the ball (joint) and pad, along with the ball (joint) and pad diameter are also measured by X-ray laminography using a 4-Pi system.

Logistic regression and multiple linear regression techniques are carried out in this study to evaluate the effects of input variables over the response variables. The logistic regression can be utilized when the response variables are coded as 0 or 1. The bridge, open, delamination open, and fatigue failure open models are analyzed by the logistic regression technique.

The thermal test cycle times to failures are coded as a continuous response variable. These models are analyzed by the multiple linear regression technique. The purpose of these models is to discover the relationships between the input variables and the time to failure under two different test cycle in the reliability failure analysis. The results obtained form these models are compared to the Finite Element Analysis (FEA) results (Riebling, J. and Pitarresi, J. M., Solder Joint Fatigue Life Prediction of Plastic Ball Grid Array Packages, 1996) generated for the selected packages.

The adequacy of each model is checked by the means of residual analysis. The coefficient of determination (R²) is used to assess the relative importance of the input variables. The high R² value indicates high relative statistical importance for each of the term in the model. The overall R² is the total deviation explained in the data set by the applied model. Normal probability plots are employed to check the normality of residuals. Classification plots are used to indicate the goodness of fit for the logistic regression models over the data set.

Solder Joint Fatigue Life Prediction Of Pbga
Abstract: This report summarizes key solder reliability modeling results as part of Universal Instruments BGA/DCA Consortium which is aimed at investigating ball grid array (BGA) and direct chip attachment (DCA) surface mount technologies from a process optimization perspective. This projects objective was to develop an understanding, through the use of computer modeling, of how the components various materials, configurations, attachment geometries, and thermal testing environments interact so that it will then be possible to optimize the process methodology with the goal of high reliability at low cost. As this report functions as an overview of the modeling work, only key results are presented. Supplementary information concerning specific modeling issues can be found in the following BGA/DCA Consortium reports: (Finite Element Modeling Issues for Ball Grid Array Components; Riebling and Pitarresi, 1995), (Power Cycling Simulation of Ball Grid Array Components; Riebling and Pitarresi, 1996), and (Effect of Solder Joint Geometry on Predicted Fatigue Life of Ball Grid Array Packages; Holub and Pitarresi, 1995).

The main thrust of the research reported herein is centered on the reliability modeling of BGA packages. A total of fifteen BGA packages, from nine different BGA configuration families, were modeled. Each was subjected to two different thermal profiles; a sixty minute, -40°C to +125°C profile, and a twenty minute, 0°C to +100°C profile. The fatigue life of the weakest solder joint from each of the fifteen packages and both thermal profiles was computed. A simple technique for the extension of the fatigue life prediction from a single joint to that of an estimate for the entire component was also developed and used on the packages modeled. For two packages, a 256 BGA and a 204 Super BGA, a power cycling simulation was performed and the fatigue life was estimated. Lastly, results from a study concerning the role that the solder joint shape has on the predicted fatigue life of a joint are presented.

Failure Analysis (Dye Penetration For Bgas)
Abstract: Electrical testing of the test assemblies gives an indication of opens in the circuit. This suggests one or more joint failures along part of a chain. Dye penetrant analysis provides an easy alternative to cross sectioning to locate the actual failures. The present report outlines the procedure.

Dca Consortium Effort
Author: Peter Borgesen
Abstract: The DCA Consortium effort was aimed at developing the Direct Chip Attach (DCA) process on the basis of current state-of-the-art technology. The primary emphasis was on ¼” flip chip with moderate pitch bumps on FR-4 substrates. However, the work considered die sizes from 0.1″ to 1.1″ with minimum pitches (center-to-center) down to about 7 mils, and substrates included FR-4, Ibiden, SLC, multilayer flex substrates and 2.5 mil thick polyimide substrates with metal stiffener rings (Direct Chip Attach Test Vehicle Designs, Primavera, November, 1996).

The present report offers an overview and discussion of the work leading up to our current process recommendations. Details of the work are covered in a comprehensive set of reports as referenced here. Based on our recommendations (DCA Assembly Process Recommendations, Huang, October, 1996; Encapsulation of DCA Devices – A Process Cookbook, Huang, October, 1996), a set of 0.062″ thick FR-4 boards were populated with a representative variety of chips and submitted to reliability testing, where they performed very well.

In terms of chip packaging, the DCA approach starts with converting a chip with aluminum alloy contact pads into a flip chip. For chips not already designed with DCA in mind this may first require the deposition and patterning of a redistribution layer and an additional passivation. Even assuming that the chips are at least available in wafer form, the cost of the necessary lithography becomes disproportionately high once they leave the wafer fab. While redistribution may help facilitate a transition to DCA until specifically designed flip chip become more available, there is therefore also considerable interest in pushing DCA to the pitches of die originally laid out for wirebonding.

Flip Chip Technology – A Review
Authors: Chien-Yi Huang and K. Srihari
Abstract: The electronics packaging industry is moving towards higher density packages to cope with market driven needs for increased product functionality and the consequent rise in component input/output (I/O) numbers. Flip Chip On Board (FCOB) technology, which involves mounting the bare die or dice directly onto the Printed Wiring Board (PWB) with solder bumps as interconnections, offers an attractive solution in terms of reduced size, cost, increased quality, and package reliability. Circuit densification can be increased because no intermediate chip packaging or lead frame is required and the whole area under the chip can be used for I/O interconnections. Flip chip solder bumping is a gang process, the strong self-alignment during reflow allows for further reductions in process cost, and the material savings from an unpackaged silicon die may be substantial. Finally, better electrical performance is expected due to the shorter interconnect length.

A review of the literature indicates that, in spite of numerous research studies and significant findings, the technology is still far from being optimized. Continuous efforts are required to achieve better quality and higher reliability while reducing costs. This report intends to serve as a first step by integrating the information provided by the relevant literature and identifying the appropriate topics for future research. The report identifies the major process steps in the flip chip assembly process and the associated issues as well as possible solutions.

Some Surface Measurement Systems
Authors: Krishna Kalyan and K. Srihari
Abstract: This report provides a review of the features available in some of the surface measurement systems that are available in the market today. The surface measurement systems that have been studied are the View 1200, View Precis, RST-Plus, View Model 880, New View 100 and the Laser MAP.

A Cost Comparison Of Dca With Alternate Packaging Technologies: Software Program
Abstract: This software based modeling tool has been developed to assist the decision maker in comparing the costs of assembling BGA’s or traditional peripheral leaded devices, such as QFP’s or TAB components, on a board against functionally comparable DCA devices. The cost model assumes that the functionality of the board used in both cases (DCA against any alternate packaging technology) does not change. The model considers several parameters such as equipment cost, depreciation, yield related costs, material costs, board costs, personnel related costs, cost of rework/repair, etc.

A Cost Comparison Of Dca With Alternate Packaging Technologies
Authors: Kumar Nagarajan and K. Srihari
Abstract: Direct Chip Attach technology has generated widespread interest in the electronics industry due to its smaller and denser interconnections, superior electrical performance, higher reliability and the potential for cost savings due to the elimination of a package. However, the current lack of adequate manufacturing infrastructure, the high cost of solder bumping and redistribution, the additional process steps needed in DCA assembly compared to standard Surface Mount Technology (SMT) assembly, and the high cost of testing for Known Good Die (KGD) are stumbling blocks in the development of this technology.

The focus of this research is to develop a methodology that would assist a decision maker with the economic justification for the use of DCA devices. The research methodology involves computing the cost of assembling a BGA or a comparable peripheral leaded device (such as a QFP or a TAB component) on a board and comparing this cost with the assembly cost of a functionally equivalent DCA device. A software based cost model, capable of estimating and computing costs, has been developed for this purpose. The cost comparisons are performed without changing the functionality of the board. While defaults are provided, the values of the cost factors considered are user defined. The software model allows the user to save and retrieve the input and output values of any previous cost analysis. This feature enables the user to perform ‘what if’ analysis. The metric used for cost comparison is the assembly cost per board. This cost model has been developed using Microsoft EXCEL software (Version 4.0).

Overview – Solder Joint Quality In A Lsi Dca Assembly
Authors: K.Naveen Kini and K. Srihari
Abstract: The presence of voids in the solder joints of a Direct Chip Attach (DCA) assembly is a concern for assembly yields and/or reliability. They might be a direct consequence of the voids that were initially present in the solder bump of the bare die itself.

Silicon dies (obtained from LSI Logic) with high lead solder bumps on them were assembled on substrates from Ibiden at Universal Instruments Corporation. A large percentage of voiding was observed in almost all the assemblies. Some electrical opens were also found. The possible causes for the formation of the voids and opens were investigated. Both problems were traced to the initial die, rather than the assembly process.

Probe Damage Of High Lead Solder Bumps
Authors: K.Naveen Kini and K. Srihari
Abstract: Solder bump deformation due to electrical probing can have a significant influence on the DCA assembly. This is because the coplanarity of the solder bumps within a same die is lost if the solder bumps are deformed. If the bumps are eutectic, then deformation may not be a major issue since these bumps melt during reflow, although problems may arise during component placement. High lead solder bumps do not melt during reflow, so here damage can ultimately result in the formation of opens. This report presents a case study of dice supplied by Motorola.

Solder Bumps On Sandia Mini-Bga Components
Authors: Naveen Kini and K. Srihari
Abstract: Wafer bumping technology involves the deposition of solder onto the pad sites of the wafer. However, depending upon the process used to deposit the solder on the pads, variations exist in the deposited solder volume. These volume variations show up as variations in the height of the solder bumps which can be disastrous from an assembly perspective. Hence, there is a need to determine if any volume variations exist between the solder bumps on an individual die.

Based on the location of the die on the wafer, the die obtained from Sandia were categorized as ‘normal’ and ‘edge’ die. Owing to the electro-deposition process used to deposit the solder onto the pads of the die, the die located at the edge of the wafer were suspected to have a larger solder volume compared to those at the center of the wafer. Higher volumes result from a high current density at the periphery of the wafer. This report provides a brief discussion on the volume and the height variations that exist between the edge die and the normal die.

Bumping Of Robert Bosch Wafers Through Stencil Printing
Authors: Kumar Nagarajan, Wilhelm Prinz von Hessen and Dana Shultz
Abstract: Wafer bumping involves the deposition of precise amounts of solder onto the die pads of a wafer. Of particular importance for the ultimate DCA assembly yield is the variation of bump height/volume across individual die. Three different types of commercial wafers, namely, CG555, CG560, and HC11, were bumped using the stencil printing process. The wafers were printed with Alpha-3060 (water soluble, type 4) solder paste using a 95 durometer polyurethane squeegee. Laser cut stencils manufactured by IRI were used for the CG555 and CG560 and a chemically etched stencil manufactured by Photostencil was used for the HC11 wafer. The printed wafers were then reflow soldered to form the solder bumps and the post-reflow residues of the water soluble paste were removed using DI water and saponifier (Alpha-2110). Following this step, the wafers were visually inspected for remaining flux residues and possible defects using a microscope. Finally, bump diameter measurements on selected die sites were used to assess typical bump volume distributions across individual die.

This report describes the process and the materials required for bumping the Bosch wafers using stencil printing. Also, the report discusses the results of wafer bumping in terms of process yield and bump volume distribution and recommends optimal stencil design dimensions.

Wafer Bumping By Solder Paste Printing
Author: Kumar Nagarajan
Abstract: Direct Chip Attach assembly yields depend strongly on the quality of the flip chip bumping process. As a final process step the bumping yield is reflected directly in the manufacturing process yield. Also, solder bump height variations across a single die may couple with board warpage and pad size variations to cause opens or bridging/satellites. Solder paste printing, together with a mask-less Under Bump Metallization (UBM) process, offers a low cost alternative to traditional flip chip bumping processes.

Solder paste printing showed considerable promise as a wafer bumping method, offering height distributions across individual die with standard deviations of 2-3% for moderate and large pitches. Substantial optimization, notably in terms of aperture shape and target solder volumes, should still be possible at finer pitches.

Characterization Of Wafers Bumped By Delco Electronics
Authors: Kumar Nagarajan , Krishna Kalyan and K.Srihari
Abstract: In general, DCA assembly yields are affected by variations in the solder volume across an individual die. This variation is significant when it is translated into the height of the solder bumps after reflow. A study of the bump dimensions was performed on wafers bumped by Delco Electronics to identify inconsistencies in the wafer bumping process. A few dice were manually measured using the Coordinate Measuring Machine (CMM) after reflow soldering. The dice had to be reflowed for this because the bumps on the die did not have a spherical shape at the time of receiving them from Delco Electronics. Also, the dice were inspected both visually and using X-ray to check for voids and defects. As received, the solder bumps on the die looked staggered as the bumps were shifted from their pads and not aligned in one straight line. Xray inspection showed the presence of voids in the bumps on some of the dice. Severe voiding caused one of the dice to fall off the board during regular handling after assembly.

Characterization Of Wafers Bumped By Aptos
Authors: Kumar Nagarajan and K. Srihari
Abstract: DCA assembly yields may be strongly affected by variations in the solder bump heights across individual die. Wafers bumped by Aptos were measured for bump diameters using an automated vision system. The heights and volumes were then calculated assuming the bumps to be truncated spheres. Significant variations in bump heights and volumes were observed. A bumping yield study was also performed.

Board Bumping And Solder Joint Shapes In First Sgs-Thomson Builds
Authors: K. Naveen Kini and K. Srihari
Abstract: Low solder bump volumes on the die were compensated by solder paste printing on the board pads to facilitate subsequent underfilling of the DCA assembly. Variations in the solder volumes deposited by printing were dominated by variations in the volume between board pad and surrounding solder mask window.

Characterization Of The Board Bumping Process (Bosch Case Study)
Authors: Naveen Kini and K. Srihari
Abstract: The solder bumping process involves the process of stencil printing solder paste onto the pads of the substrate followed by subsequent reflow. The variation in the solder paste volume that is deposited during stencil printing can cause major concerns when it is translated into the height of the solder bump after reflow. A case study, a design of experiment analysis was performed on the BOSCH boards (supplied by HADCO, bumped at Universal Instruments Inc.) to understand some of the important printing and board related parameters that could cause variations in the solder paste volume deposits on the board. Some of the factors analyzed were the print direction, pad sizes, pad metallurgy, site locations on the board, pin location and aperture orientation. The results obtained from the statistical analysis indicated that even though most of the sources which could cause the variation in the solder paste volumes have been identified and compensated for in the subsequent analysis, the impact of print direction, pin location and the aperture orientation effect still exist. Printing experiments conducted on a bare laminate helped to eliminate the pin location effect. The print direction effect was indeed significant, but can be compensated. The volume measurements obtained from the SVS were validated through cross-sections of the coined bumps. Volume of the solder bumps from the cross-sections indicated that the volume of the solder paste that is hidden in the gap between the solder mask and the pad (unaccounted in the SVS 7530 measurements) is significant. It is one of the factors that could explain the solder volume variations within the die sites and between the various prints.

Surface Evolver A Tool To Model Solder Bump & Solder Joint Shapes
Authors: K. Naveen Kini and K. Srihari
Abstract: One of the fundamental problems in the calculus of variations is to find a surface minimizing some energy subject to constraints. The Surface Evolver (Brakke K.,1992, Version 1.99) is a program developed at the Geometry Center, Minneapolis & Susquehanna University, capable of generating surfaces shaped by surface tension and other energies. This software requires an initial surface to be defined by the user in a datafile. The evolver evolves the surface towards minimal energy by a gradient descent method. The energy in the evolver can be a combination of surface tension, gravitational energy or any other user-defined surface integrals. The Evolver has the capability to handle arbitrary topology, volume constraints, boundary constraints and gravity. The user can interactively modify the surface to change its properties or to keep the evolution of the surface under control.

The Surface Evolver software is freely available and is public domain. It can be directly acquired from the Internet (Do an ftp login to geom.umn.edu as “anonymous” with your e-mail address as password). For the PC compatibles, there is a 32-bit DOS version “pub/software/evolver/evolver.zip”. This PKZIP archive contains the executable file for this software, ”evolver.exe”, the DOS extended program needed to run it, and a few data files) (Brakke K.,1995).

Solder Volume Estimation For Solder Bump Coplanarity (Kodak Case Study)
Authors: Naveen Kini and K. Srihari
Abstract: In general, DCA assembly yields are affected by a combination of solder bump height distributions and substrate warpage. The shape and height of a solder bump depends upon a number of constraints which relate to solder volumes, pad sizes and pad shapes. For the same pad size and shape on a single individual die, the solder volume variation is the most significant factor that influences the coplanarity of the solder bumps. However, when the pad sizes and shapes are designed to be different on the same die, the solder volumes that need to be applied on the individual pads are now also different. In this case, deviations from the target solder volumes become even more significant. This report describes the methodology used to determine the solder volumes that need to be deposited in order to maintain coplanarity of the solder bumps in such a case. A case study on Kodak die is discussed.

Characterization Of The Drum Fluxer
Authors: Sarathy Rajagopalan and K. Srihari
Abstract: The drum fluxer only applies the flux where it is needed, thus minimizing residue for those fluxes where it works. The performance of fluxes with viscosities between 58 and 510 Kcps on the drum fluxer was briefly characterized. Low viscosity fluxes tend to wick up the joints and spread on the die surface. This may be minimized by limiting the dip time. Higher viscosity fluxes perform well at 2-3 mil dip depth. In this case 400-600ms of dip time is optimum.

Direct Chip Attach Fluxes Testing And Evaluation
Authors: Sarathy Rajagopalan and K. Srihari
Abstract: In the DCA assembly process fluxes are used to remove oxides and to provide the necessary tackiness to hold the component until reflow. The present report summarizes work done to characterize the fluxes considered for this purpose. Most of the material contained here may also be found in the BGA solder paste report (Solder Paste Testing and Evaluation, Rajagopalan & Srihari, 1996).

Direct Chip Attach Test Vehicle Designs
Authors: Anthony Primavera and Ya-Ping Lin
Abstract: In an effort to focus on assembly of flip chip die onto low cost substrates, the DCA Consortium test vehicles were designed and fabricated using conventional printed circuit board technology. Test vehicle die were obtained from various sources, including commercial vendors and Consortium Principals, and were fabricated by UIC staff at the National Nano-fabrication Facility at Cornell University. Die include perimeter array, full array, staggered perimeter array, and non-uniform designs. Designs included die converted from wirebond designs, redistributed patterns and die designed specifically for flip chip. Functional as well as test chips were used throughout the study. Test chips included simple daisy chain stitched patterns as well as die embedded with various sensors and monitoring capabilities. Functional die applications included automotive, telephony, and consumer products. Several fully functional applications were assembled and tested as part of the Consortium interaction with the Principal members. This document is a summary of several test vehicle designs utilized in the project.

Contact Pad And Solder Mask Variations Across A Panel Of Fr-4 Boards For Dca
Authors: Krishna Kalyan and K. Srihari
Abstract: This study evaluated the registration of the solder mask over three boards used in a specific Northern Telecom assembly. The distributions of (i) the difference between the centers of the solder mask windows and the centers of the pads, (ii) the width of the solder mask openings (iii) the minimum distance between the edges of the solder mask openings and the edges of the pads, (iv) the width of the exposed traces, (v) the length of the exposed traces and (vi) the pad area were determined for the pads in the die area on three boards of a panel. The results were compared to the Gerber (design) data. A systematic shift in the X direction was observed.

Characterization Of Ibiden Substrates
Authors: Krishna Kalyan and K. Srihari
Abstract: Substrates from Ibiden Corporation were characterized with respect to the diameter of the pads, the length of the exposed traces, the registration of solder mask, the moisture absorption/desorption characteristics, and the warpage at room and reflow temperatures. An experimental procedure was developed to measure the warpage at reflow temperature. The effect of different substrate carriers on the warpage was found to be minor. Shadow Moiré interferometry was performed on two substrates to understand the variation of warpage with temperature.

The warpage in the die region of the substrates was generally towards the Ball Grid Array (BGA) side during and after reflow. The warpage at reflow temperature was usually close to the warpage at room temperature after reflow.

Characterization Of Slc Substrates
Authors: Krishna Kalyan and K. Srihari
Abstract: This report characterizes a batch of SLC substrates manufactured by IBM with respect to variations in pad sizes, solder mask openings, warpage, and thickness within the die region. Variations in thickness of up to 2.5 mils were observed within the die region of these substrates. The warpage within the die region ranged between 0.5 mils and 1 mil, while the warpage over the entire substrate ranged between 0.5 mils and 3.0 mils.

Effects Of Board Parameters On Dca Assembly
Authors: Naveen Kini and K. Srihari
Abstract: The miniaturization witnessed in surface mount assembly has reduced process windows. This is especially true in the direct chip attach domain with respect to the variations seen in board parameters. The variation in board parameters can impact the height of the solder bumps that are formed through the board bumping process. Even if the bumps are coined before assembly, variations in the reflown heights may combine with variations in the chip bump heights and board warpage to provide open joints. The shape and height of the solder bumps on the board can be influenced by variations in the (i) volumes of the solder paste deposits, (ii) pad diameter, (iii) diameter of the solder mask opening, (iv) exposed trace length, and (v) the solder mask registration. It is necessary to understand the combined influence of all these variations.

In this report, the impact of variations in board parameters and solder volumes on the heights of the solder bumps is illustrated through a case study. The height of the solder bumps has been determined using the “Surface Evolver” software. The shape of the solder bumps has been modeled for a variety of board parameters and solder paste volumes. An approach to determine the factor with the greatest impact on the height of the solder bumps has been developed.

Dca Substrates And Placement Tolerance
Authors: Yu-Wen Huang and K. Srihari 
Abstract: Due to the small pad size, bump size, and bump pitch, in-plane variations are critical for DCA assembly. A computer based simulation software using a Monte Carlo approach was developed to simulate the inplane variations. The assumption of an inscribed circular pad geometry represents the worst case scenario. The simulation results indicated that solder mask registration has a significant impact on placement yield. Also, machines with less placement accuracy and repeatability of course required a larger placement target (larger pad size) than those with higher accuracy and repeatability. Board bumping (through a stencil printing process) that results in enlarged coined bumps on the substrate increases the placement tolerance. However, board bumping is pitch dependent and additional process steps (coining and cleaning) are needed. Finally, a preferred pad design, which should result in a low defect level, was suggested.

Prediction Of Out-Of-Plane Solder Joint Defect
Authors: Yu-Wen Huang and K. Srihari
Abstract: The combined effects of component and board warpage during reflow, together with solder volume and pad size variations, may lead to opens, satellite formation, or bridging in BGA assembly. In DCA assembly some of these variations are, of course, negligible but because of the smaller tolerances the remaining effects are still critical. A Monte Carlo based computer program has been developed to predict assembly yields on the basis of statistical variations in the various parameters.

Assembly Yield Predictions And Design Issues For Bosch Dca
Authors: Santhana Satagopan and K. Srihari
Abstract: Assuming sufficient placement accuracy, DCA assembly yields generally depend on variations in board warpage, pad sizes and solder volumes on chip and board. Sensitivity studies were carried out for a specific case to illustrate how acceptable process windows may be defined. A Monte Carlo based simulation program was used to predict the effects of individual parameters on the assembly yields for DCA of a 0.2″ die with 25 I/O onto regular FR-4 boards. Acceptable yields should be achievable without board bumping for realistic board warpages and bump volume distributions.

Monte Carlo Simulation Based Yield Predictions For Dca Assembly On Ibiden Substrates
Authors: Santhana S. Satagopan and K. Srihari
Abstract: The effects of bump volume distributions on chip and substrate in a specific DCA assembly were assessed by means of a Monte Carlo based computer program. The assembly simulated consisted of a large (15 mm) die attached to a substrate with a realistic warpage at reflow temperature. The process is seen to require board bumping and/or a limited board warpage, tight bump volume distribution and redesign of the die pads.

Pad Design Guidelines For Direct Chip Attach Assembly
Authors: Naveen Kini, Krishna Kalyan and K. Srihari
Abstract: Variations in solder bump volumes, solder mask windows and pad sizes across a die site may significantly affect DCA assembly yields. However, the sensitivity to such variations can be minimized by proper design of the contact pads on chip and substrate. Taking also placement concerns into consideration design recommendations are made for use in assembly processes with and without board bumping.

Robert Bosch Dca Assemblies
Authors: Wilhelm Prinz von Hessen, Yu-Wen Huang, Ravi S. Pitchika and Chien-Yi Huang
Abstract: One-quarter inch die with solder bump pitches down to 8.5 mil were assembled onto FR-4 boards and underfilled. Potential advantages and disadvantages of board bumping by stencil printing were assessed, but all subsequent investigations were pursued without board bumping. Encapsulant delamination during Liquid-to-Liquid Thermal Shock testing was found to depend on solder mask, organic solder protect, flux type, chip layout, moisture and process conditions in non-trivial ways. A process was developed and qualified for the ‘drop-in’ replacement of a standard SMT component by Direct Chip Attach (DCA) for an automotive application.

Assembly Development Of Direct Chip Attach With Eutectic Pb-Sn Solder Bumps On Organic Substrates
Authors: Abhay Maheshwari and Sunil Thomas
Abstract: Direct Chip Attach (DCA) on Printed Wiring Boards (PWB) is gaining increased popularity these days, especially for applications requiring high I/O in relatively small areas. As the I/O count increases and the area available decreases, DCA becomes a very efficient way of miniaturizing PWB assemblies. The process development and implementation of DCA assemblies pose a challenge to the industry, since very little information is available about the intricacy of the process.

This report gives an overview of direct chip attach on organic printed wiring boards. The report is based on the work performed in developing area array packages using DCA technology. It describes wafer bumping, PWB structures, assembly processes, and underfilling. Various areas of concern (both assembly and reliability) are addressed and briefly discussed. The report also talks about process variables associated with DCA technology and how careful evaluation of these variables can lead to zero defect assembly. This report is intended to help the process development as well as the manufacturing engineer understand the steps involved in implementing DCA.

Dca Assembly Process Recommendations
Authors: Yu-Wen Huang and K. Srihari
Abstract: Small dimensions and tight tolerance requirements for DCA impose stringent variation control on each assembly process step involved. In order to develop the DCA assembly process, both theoretical (computer based simulation) and experimental approaches were used. Based on the simulation and experimental results, the recommended DCA assembly process as well as assembly process windows were made. The suggested DCA assembly process includes fluxing, placement, reflow, and underfill. By using the drum fluxer which can be incorporated into placement operation, the DCA assembly process was found compatible with the standard surface mount assembly process. High placement accuracy and repeatability were required for DCA due to small feature dimensions and tight tolerances. The reflow profile parameters were found to be compatible with those for BGAs.

The Dca Assembly Experiments
Authors: Yu-Wen Huang and K. Srihari
Abstract: A series of DCA assembly experiments were conducted to supply product for reliability testing. The assembly process included fluxing using the drum fluxer, component placement, and reflow soldering. By combining fluxing and component placement operations, the DCA assembly process can be included within the standard surface mount PCB assembly process. Important assembly process issues were investigated. These issues included die size, flux type, flux depth, board thickness, board pad metallurgy, and reflow type. General observations based on the DCA assembly experiments are as follows.

  • Flux is used in the DCA assembly to chemically induce wetting and to hold the die in place during processing. A flux depth of 0.0015″~0.002″ seems to be the lower limit in the fluxing operation. If the flux dip depth is more than 0.0025″, it might have a negative impact on underfilling.
  • Accurate component placement can be achieved by using the machine vision assisted local fiducial placement method. Nozzles used in the placement machine need to be carefully selected to prevent ‘die movement’ during placement.
  • Both the IR and the forced convection ovens were found to be adequate for use in the DCA reflow soldering process.

Some Initial Experiments For The Assembly And Underfill Of Lsi Dca Packages
Authors: Chien-Yi Huang and K. Srihari
Abstract: Initial experiments were carried out for the assembly and underfill of the DCA components provided by LSI Logic. A study was performed to examine some assembly parameters. This resulted in the variation in the package standoff height as well as the amount and location of the flux residues. The assembled packages were then underfilled using two encapsulants. Samples were inspected using the Scanning Acoustic Microscope (SAM) for the completion of the underfill and for the formation of voids beneath the chip. An X-ray system was used to inspect the quality of solder joints. Three primary assembly related defects were identified and discussed. Cross-sectioning was also used along with SAM and X-ray analysis to complete the inspection efforts. These two encapsulant materials were compared with respect to their tendency to form voids, their underfill process parameters and the time to complete the capillary flow. The effects of the amount of flux residue on the formation of voids during underfilling was also examined and discussed.

Assembly Of The Mms Blackbird Substrate
Authors: Sarathy Rajagopalan and K. Srihari
Abstract: In continuation of previous development work on a specific DCA assembly with Texas Instruments (Maheshwari & Thomas, 1996), initial experiments were conducted on an alternative substrate from MicroModule Systems intended for the same application.

The Blackbird assembly is a Ball Grid Array (BGA) consisting of an underfilled flip chip on a flex substrate supported by a stiffener ring. The 34.86 mm square substrate produced by MicroModule Systems (MMS) consists of a 2.5 mil thick polyimide decal and a 50.5 mil thick aluminum stiffener (Comparison of Litronic and MMS Flex Substrates for the TI DCA Assembly, Gurumurthy & Srihari, February 1996). The pad configuration is the same as described elsewhere for the TI substrate (Initial Study of an Underfill Process for the TI X1470 Chip, Huang & Srihari, July 1995). The 0.5″ square die is polyimide passivated and has 1064 I/O on a 10 mil pitch. Initial tests were conducted with 5 die received from Texas Instruments, while all other die were produced by Aptos.

Warpage Of Northern Telecom Flip Chip Assemblies
Authors: Charan Gurumurthy and K. Srihari
Abstract: Forty flip chip components were considered in this warpage related study. Warpage was measured at room temperature after the underfill process. While some of the silicon die showed a strange surface profile, an extremely high level of variation was seen in the warpage data gathered from one assembly to another. Currently these observations have no explanation.

Warpage Of Ti Dca Substrates And Assemblies
Abstract: Beam theory was used to calculate the warpage of DCA flex substrates and assemblies after cool down from the cure temperature of the underfill. The analysis was used to assess the sensitivity to various materials and design parameters for a particular assembly design, and potential remedies minimizing warpage were proposed. While beam theory might not provide exact values of warpage even in the absence of inelastic effects (creep), it offers insight into systematics and sensitivities. A validation of the estimates was achieved by comparing predicted warpage to experimental measurements.

Litronic & Mms Flex Substrates Comparison
Authors: Charan Gurumurthy and K. Srihari
Abstract: Substrates provided by two different sources (Litronic and MMS) were reviewed with respect to their use with a TI DCA component. Warpage of the assembly was used to distinguish between these two substrates. Both the substrates are flex thin film substrates made up of polyimide. This report compares the warpage issues on the various regions of the two substrates. After DCA assembly (including underfill), the MMS substrate showed less warpage. Also, problems associated with the uneven thickness of the solder mask on either side of some of the Litronic substrates were totally eliminated with the MMS substrate. The MMS substrates show a shrinkage slack of up to 7 mils (before underfill). This was not seen in the Litronic substrates, but is not believed to have negative consequences anyway. The warpage behavior over the stiffener ring region of both types of substrate is similar. Unlike the Litronic substrates, analysis suggests that the MMS substrate based assemblies are sensitive to modulus, CTE and thickness of the underfill, but less sensitive to variation in the modulus and CTE of the substrate.

Warpage In Dca Test Vehicles
Authors: Krishna Kalyan and K. Srihari
Abstract: Warpage of the test vehicles used in the Direct Chip Attach (DCA) consortium was measured in three stages, namely, the warpage of the test boards as received, after placement and reflow, and after prebaking. The warpage along the diagonal of a 1/4″ die region on the 62-mil thick test boards was about 0.20 mils, while the warpage in the die region on the 18-mil thick boards was about 0.30 mils.

Effects Of Surface Features And Defects On The Fracture Of Silicon
Authors: Charan Gurumurthy and K. Srihari 
Abstract: Observations of die cracking in DCA assemblies during handling and thermal shock testing have been ascribed to the effects of surface and dicing defects under thermal mismatch induced warpage. Indeed, die fracture was more commonly observed on 20 mil thick FR-4 boards and the Litronic substrates tested by Texas Instruments than on regular 62 mil thick FR-4. The fracture of different die types was investigated by three point bending. While the cracking of die with severe dicing defects was occasionally observed at realistic curvatures, and warpage might indeed contribute to the fragility of defective die, the reported frequency of die cracking during thermal shock could not be explained by our results. It appears that such observations reflect the presence of other defects that are not sensitive to pure bending.

Moisture And Board Effects On Underfill Encapsulants
Author: Thomas Driscoll
Abstract: Studies on encapsulant curing are usually done under idealized conditions. In a real DCA assembly, however, small amounts of moisture in the board, as well as the mere presence of the board itself, may affect the curing of the encapsulant, and thus the resulting properties. Examples of such effects on cure kinetics were investigated by Differential Scanning Calorimetry. For three of the four encapsulants studied, the glass transition temperatures of the final products were reduced by the presence of the board/solder mask during cure. Also, subsequent moisture absorption into the cured material may, of course, pose problems in terms of popcorning, etc. The kinetics of moisture absorption was therefore studied by monitoring the weight gain with time.

Examination Of The Coefficient Of Thermal Expansion Of Underfill Encapsulants
Author: Thomas Driscoll
Abstract: The bulk coefficient of thermal expansion and glass transition temperature were determined using a thermal mechanical analyzer (TMA) operated at 10°C/min between 25°C and 255°C. Both samples cured in open (to the atmosphere) containers and in sealed containers were examined. The majority of the CTE values obtained were greater than the CTE values quoted by the vendors. The majority of the glass transition temperature values for samples cured in sealed containers were greater than the glass transition temperature values as stated by the vendors or found via DSC. The majority of the glass transition temperature values obtained for the open cured samples were significantly lower (typically > 20°C difference) than the values stated by the vendors.

Examination Of The Cure Behavior Of Underfill Encapsulants
Author: Thomas Driscoll
Abstract: The curing reactions of the underfill encapsulants were studied using Differential Scanning Calorimetry. Characteristic properties of the encapsulants were obtained from simple analysis of the data. These properties are good for comparative purposes. Modeling of the rate of conversion was attempted, but a rate of conversion equation has yet to be obtained due to the complex nature of the curing reactions.

Room Temperature Viscosity Measurements Of Underfill Encapsulants
Author: Thomas Driscoll
Abstract: The room temperature viscosity of underfill encapsulants was measured using coaxial cylindrical geometry. The majority of the encapsulants exhibited pseudoplastic behavior. Deviations from this behavior were noted for some encapsulants at particularly low shear rates (< 1 s-1). Such deviations are most likely the result of the filler in the encapsulants. Viscosity measurements of some of the encapsulants indicate a flow behavior that is opposite of the flow behavior seen at 70°C for a 4 mil stand off, indicating that room temperature viscosity measurements are not good indicators of flow behavior.

Issues In Filler Settling For Encapsulant X
Authors: Jacek Knop and K. Srihari
Abstract: Studies of particle settling in encapsulant X were conducted in order to determine whether or not the silica particles have a tendency to settle during the underfill and cure processes. The examination involved numerous underfill temperatures, gel temperatures, and cure positions. We also examined the particle settling in a “new and improved” version of encapsulant X. This study concluded that particle settling occurs during the cure process and that it is possible to stop the settling by curing the assembly vertically. It was shown that the new version of encapsulant X also settles, in spite of the reduced size of the filler particles.

The Flow Behavior Of Epoxy Resin Encapsulants @ 80″C
Author: Thomas E. Driscoll
Abstract: The flow of encapsulants considered for underfilling DCA assemblies was examined at 80°C using a model flow experiment consisting of two surfaces offset by a predetermined amount. Stand off heights considered were 1 – 5 mil (0.0254 – 0.1270 mm). The flow behavior was analyzed assuming surface tension driven laminar flow of a liquid. Theory predicts a direct proportionality between stand off height and flow velocity, but an offset in the stand off height dependence was observed. This offset is attributed to the filler particles in the encapsulant.

Flow Model Of Encapsulants: Incorporation Of The Presence Of Fillers
Author: Thomas Driscoll
Abstract: In an industrial underfill encapsulant, large percentages by weight (or volume) of a filler material, generally silica, are added in order to lower the coefficient of thermal expansion of the cured encapsulant. Previous attempts have been made to model the flow of this highly filled system as both a Newtonian and NonNewtonian liquid. However, these models are unsuccessful in predicting several trends that have been observed experimentally. A model is constructed where the presence of the filler material is taken into consideration. The filler material is represented as rectangular boxes all of the same dimension, with the same spacings between each filler box. The fluid these boxes move with is assumed Newtonian. Taking this simple view of a suspension, an equation is derived that predicts the general flow behavior of the encapsulants and experimentally seen trends: 1) linear flow distance squared versus time, 2) linear velocity factor versus stand off height, and 3) non-zero intercept of velocity factor versus stand off height.

Capillary Flow Of Three Encapsulants: Temperature Dependence And Repeatability
Authors: Jennifer Fosberry and Thomas E. Driscoll
Abstract: The repeatability of the capillary flow of two encapsulants (J and P) was investigated. The repeatability of Encapsulant J was tested with and without the use of thermal grease to provide a good thermal connection of the flow setup to the heating block to determine the importance of good thermal contact. The impact of temperature drift during the repeatability tests of Encapsulant J was also studied. The repeatability of Encapsulant P was studied after one hour thaw and again after six hour thaw. Temperature dependencies of Encapsulants J, N, and P were determined, along with their respective activation energies. For Encapsulant P the flow distance was seen to vary faster with time, t, than the square root t dependence predicted for non-Newtonian liquids, suggesting a strongly dilatant behavior at shear rates near and below 1 inverse second. Still, no major trend of power dependence on temperature was determined, thus the activation energy of Encapsulant P was also determined. Parameters of an analytical flow expression were also calculated.

Capillary Flow Of Encapsulants: Effects Of Surface Tension And Contact Angle
Authors: Jennifer Fosberry and K. Srihari
Abstract: Understanding and being able to describe the underfill process of Direct Chip Attach (DCA) technology is important in optimizing materials and parameters. In this study, an equation for capillary flow of a liquid between two semi-infinite parallel plates was derived. The predicted dependence on contact angles with the solid surfaces was verified experimentally. Contact angles of one encapsulant (Encapsulant D) on a number of relevant surfaces (polyimide, silicon oxide, silicon wafer, glass slides, solder mask, copper, FR4, Teflon board, and Teflon tape coated glass slide) were measured, and effects of time, substrate conditions and temperatures, as well as preceding time at ambient temperature, were determined. Contact angles of two different batches of another encapsulant material (Encapsulant H) on some of the same surfaces were also determined at two different temperatures. The contact angles of encapsulants A, D, E, F,G, H, I were determined on three surfaces (Polyimide, Silicon Oxide, and Solder Mask). The surface tensions of fourteen of the encapsulants (Encapsulants A, B, C, D, E, F, G, H, I, K, L, M, N, and O) were measured at ambient temperature and predicted effects on capillary flow discussed. The effect of fillers on the surface tension was investigated by comparison with results for an unfilled encapsulant. The surface tension of Encapsulant E was measured as a function of room temperature aging and “thawing” time. Finally, the effect of contact angles on fillet formation was discussed.

“Capillary Flow Of Encapsulants: The Dependence Of Flow On Temperature, Standoff, And Surface Morphology”
Authors: Jennifer Fosberry and K. Srihari
Abstract: Three encapsulants that flowed rapidly during the initial screening experiments were subjected to further study. The flow behaviors of these materials were examined at three temperatures, three standoffs, and two surface morphologies. Not only did the observed dependencies on these parameters not agree with our capillary flow model, they also suggested interactions between them all.

Capillary Flow And Void Formation Of Encapsulant V
Authors: Jennifer Fosberry and K. Srihari
Abstract: Initial screening tests showed Encapsulant V to flow quite rapidly, but to form large voids when cured between two solid surfaces. Subsequent investigations showed void formation to vary with cure temperature, but significant voiding was observed for all vendor recommended cure profiles.

“Capillary Flow Of Encapsulants: Dependence On Surface Morphology, Standoff And Time”
Authors: Jennifer Fosberry and Thomas E. Driscoll
Abstract: The capillary flow of various encapsulants (D, E, F, N, O, P, and Q) was measured as a function of standoff. One material exhibited a sufficiently non-Newtonian behavior to produce a measurable deviation from the usual variation of flow distance with the square-root of time. This deviation appeared to increase with decreasing standoff and with increasing roughness of the solid surfaces. A similar deviation was also observed for other materials on rough surfaces. Flow velocities varied significantly between encapsulants and the flow of various encapsulants exhibited quite different sensitivities to standoff and surface roughness. An empirical relationship between flow distance, time, standoff and temperature was proposed, based on analytical models, and some of the parameters were determined for various materials by fitting to available data.

Gelation In The Capillary Flow Of Encapsulants L And X
Authors: Jennifer Fosberry and K. Srihari
Abstract: Encapsulants L and X were studied for onset of gelation at different temperatures. Gelation was defined as the time when flow velocity started to decrease faster than inversely proportional to the flow distance. As the flow temperature increased, the time to gelation decreased and became more regular (i.e. less variation), as expected. The time to gelation increased with smaller standoffs, but was smaller for flow between smooth and frosted glass slides than for flow between smooth surfaces.

“Variations In Capillary Flow And Room Temperature Viscosity Of Encapsulants E And X: Within A Batch, Over
Several Batches, And Over The Storage Age Of The Material”

Authors: Jennifer Fosberry and K. Srihari
Abstract: The flow behaviors of Encapsulants X and E for flow between smooth and frosted glass slides separated by three mils at a relevant temperature (100°C and 75°C, respectively) were investigated for variations within a batch on the same day, within a batch over the storage age in the freezer (-65°C), and across several batches. The behavior of the velocity factors were compared with room temperature viscosities taken at a shear rate of 2.5/sec.

Encapsulant E was essentially the same in two separate batches according to tests conducted by two separate investigators.

For Encapsulant X, batches of similiar age yielded similar results, but storage age impacted the material in an unexpected fashion. While the viscosity increased, as expected, the velocity factor increased as well. This was explained by a reduction in the amount of filler settling in the aged materials leading to fewer particles in the flow samples, but not in the larger volume viscosity samples.

Capillary Flow Of Encapsulants: Statistical Distribution Of Velocity Factors
Authors: Jennifer Fosberry and K. Srihari
Abstract: An experiment was designed to obtain an idea of the distributions of the velocity factors for encapsulants. Possible experimental causes of the variation in the velocity factors were considered. It was determined that the uncertainty in the factor levels (i.e. standoff and temperature), and the use of two aluminum heating blocks could not cause the experimental scatter observed in the velocity factors. Many replications of the flow of Encapsulants X and L between a smooth and a frosted glass slide separated by three mils at relevant temperatures, show that a normal distribution represents the data very well and that this assumption can be made for other materials and test scenarios. Also, an idea of the magnitude of the effect that room temperature aging has on the velocity factor was obtained.

“Capillary Flow Of Encapsulants: The Dependence Of Statistical Scatter On Standoff, Temperature, urfaceMorphology, And Room Temperature Aging”
Authors: Jennifer Fosberry and K. Srihari
Abstract: The statistical uncertainties in flow at the various factor levels (standoff, temperature, and surface morphology) were quantified over room temperature age. When the velocity factors were corrected for room temperature aging, the means increased, as expected, but in many cases these corrections did not greatly affect the standard deviations. In general, the scatter tends to scale with the flow velocity itself.

Encapsulant Screening Procedure
Authors: Jennifer Fosberry and K. Srihari
Abstract: Initial experiments (flow, voiding, contact angle, process) performed on seventeen materials led to an idea of acceptable levels of encapsulant performance. In light of this experience, a screening procedure was developed to rapidly screen incoming materials. A quick experiment was developed to screen several important encapsulant behaviors at once. The experiment was run on the original materials to validate this procedure, before it was applied to current materials. Of all the materials tested, twelve passed and eighteen failed.

Encapsulant Flow Rate Measurement At Various Preheat Temperatures
Authors: Chien-Yi Huang and K. Srihari
Abstract: The DCA encapsulation process involves the dispensing of a filled epoxy resin with a CTE that is compatible with that of the solder joints. The encapsulant is usually dispensed near the edge of the chip, and its flow occurs by capillary action. The long encapsulant dispensing process cycle is one of the factors which inhibits the high volume use of the DCA technology.

Experiments are done to explore the effect of the substrate preheat temperature on the encapsulant flow. The effects of increased substrate temperature on material gelling are addressed, and the occurrence of defects due to the use of higher preheat temperatures is evaluated. The data collected is compared with theoretical deductions. This report presents initial results for the Encapsulant D at temperatures between 60C and 110C.

Effects Of Encapsulant Aging And Surface Morphology On The Flow Rate
Authors: Chien-Yi Huang and K. Srihari
Abstract: The DCA encapsulation process involves the dispensing of a filled epoxy resin with a Coefficient of Thermal Expansion (CTE) that is compatible with that of the solder joints. The encapsulant is usually dispensed near the edge of the chip, and flow occurs by capillary action. The development of a robust encapsulation process requires an effective estimate of the time required for a given amount of material to complete capillary flow. While independent values for shelf and pot life are usually specified by the vendor, it is here important to realize that material flow characteristics (such as viscosity) do, in fact, depend on aging in storage, in the dispenser and during flow at elevated temperature in a cumulative fashion.

Experiments were conducted to explore the effect of room temperature aging on encapsulant flow through the suggested pot life. As expected, the effect depends on the chip-size (flow distance) considered. A substantial experimental variability was ascribed to surface roughness of the solder mask sample and a model experiment performed to confirm this. Unlike simple liquids, the filled encapsulants flow slower on rough surfaces than on smooth ones. The sensitivity to surface roughness did, however, depend quite strongly on the encapsulant.

The Encapsulation Of Dca Devices – A Process Cookbook
Authors: Chien-Yi Huang and K. Srihari
Abstract: This report provides a “cookbook” for the underfilling of DCA devices. Recommendations are made as to materials selection and process development. Details, explanations and background are found in references.

The Underfill Process For Bosch And Northern Telecom Dca Assemblies Some Initial Experiments
Authors: Chien-Yi Huang and K. Srihari
Abstract: Initial experiments that were carried out to underfill DCA components provided by Bosch and Northern Telecom are described. Two types of encapsulants, E and J, were used to underfill these DCA components after assembly. Encapsulant was dispensed along one edge without dispensing the exit fillet. Multiple passes (four passes) were used to dispense the encapsulant in order to minimize the size of the encapsulant entrance fillet and to prevent the material from flowing on to the top of the chip.

The time between individual passes was based on the visual observation of the encapsulant material that was present at the edge of the chip when the encapsulant dispensed in a pass completed its flow. The appropriate time between dispensing passes was then determined. The results obtained were compared to the data collected in prior model experiments, and inferences were drawn. The possible contamination of the solder joint and the chip site with flux residue and the formation of interior voids in the encapsulant were two defects that were observed. The causes of these two defects are discussed in this report.

The Dca Encapsulation Process
Authors: Chien-Yi Huang and K. Srihari
Abstract: This report provides an overview and summary of numerous reports on various aspects of the DCA encapsulation process. The procedures suggested are based on inferences drawn and models developed in these. Recommendations are made as to equipment selection criteria, materials selection, receiving and inspection, and underfill process development.

A Model For Optimizing The Underfill Substrate Temperature
Authors: Chien-Yi Huang and K. Srihari
Abstract: The typical underfill dispensing cycle includes the time needed to complete the capillary flow. The long dispensing cycle is one of the factors which inhibits the high volume use of DCA technology. The preheat of the substrate is recommended by the vendors of underfill material as a mechanism to help achieve better flow characteristics and reduced flow times. The preheat temperatures that are usually suggested by vendors vary slightly and are in the range of 70°C to 80°C. This recommendation is somewhat arbitrary, and should be application dependent. This study evaluates the feasibility of using a higher substrate preheat temperature to reduce the process cycle time, and systematically determines an optimal substrate preheat temperature.

Some defects that can be induced by the high substrate preheat temperature, including filler settling and voiding, were evaluated. No significant defect was observed due to the use of higher substrate preheat temperatures. Other possible impacts such as interface adhesion and the package reliability will be evaluated in the near future. Besides, material flows faster at a higher temperature and gelling occurs earlier. Therefore, one major concern when using a high substrate preheat temperature is to ensure that the flow of underfill material is completed before gelling begins. Experiments were done to characterize the flow behavior of an encapsulant. A statistical model was developed to determine the probability of the occurrence of a good underfill (flow complete before gelling begins). By setting a criteria (6σ), an optimal substrate preheat temperature for a given scenario was determined.

Initial Study Of An Underfill Process For The Ti X1470 Chip
Authors: Chien-Yi Huang and K. Srihari
Abstract: An initial study to characterize the underfill process for a specific application is described. The package considered in this research has a single chip which is passivated by a polyimide layer. The chip is mounted on a polyimide (flex) substrate covered with a solder mask. The substrate has a copper stiffener ring to ensure the rigidity of the package. The stiffener has an opening at its center. The chip is located inside this opening. The chip has 1064 I/Os and the various batches of assemblies had standoff heights of 2.5~3.5 mils.

Various encapsulants were evaluated with respect to flow rate, wetting performance, and exit fillet formation. Appropriate candidates were then selected based on the results of this and the information provided by vendors. Some dispensing related process parameters were also identified.

Four different batches of assemblies were underfilled. The batches differed in the chemical composition of the substrate surface, the surface texture, and the stand-off height. Four batches were used to evaluate different encapsulants and process parameters. The assembled (underfilled) packages were inspected and defects were identified. Results were compared to data obtained underfilling another, more “conventional” DCA assembly.

A Model Evaluating The Dispensing Pattern For The Underfill Process
Authors: Chien-Yi Huang and K. Srihari
Abstract: The dispensing pattern for the underfill process is one factor which determines the process cycle and may have an influence on the reliability of the package (or the defect level). An ‘L’ shaped two edge dispensing pattern was found to reduce the time needed to complete the capillary flow by 30% when compared to a single edge dispensing pattern. However, voids were more frequently seen at the diagonal corner away from the dispensing edges when an ‘L’ shaped two edge dispensing pattern was used.

Factors that influence the formation of voids were identified. They include the flow front angle, the perturbation of the flow front, the location of the perturbation, and the chip size. These parameters were measured as a function of the flow distance. The standoff, surface roughness, and material dependency were studied with respect to the irregularity and the angle of the flow front. A statistical model was developed to predict the probability of void formation. Reasonable assumptions were made to simplify the model. The proposed model estimates that there is a 22% chance of void formation when a two edge dispensing pattern is used with Encapsulant E for a half inch square chip. Unacceptable yields were predicted for all chip sizes and encapsulants. This estimate agrees with the observations made during previous underfill experiments.

Finite Element Modeling Of Dca Assemblies Task 1: Unencapsulated Dca Studies
Authors: Jeff Riebling and James M. Pitarresi
Abstract: This report summarizes solder reliability finite element modelingefforts as part of Universal Instrument’s BGA/DCA Consortium. The main thrust of the research reported herein is centered on the solder joint fatigue life estimation for unencapsulated DCA packages. Perimeter and full area unencapsulated DCA packages were modeled. For the perimeter array, various die sizes, die and printed circuit board (PCB) thicknesses, and standoff heights were modeled. The die sizes that yielded relatively low predicted fatigue lives for the perimeter array were then modeled as full array packages and the fatigue life predicted. The thermal profile used in all simulations was a 0C to +100C twenty minute cycle with five minute ramp and dwell times. The methodology used for the joint life prediction is based on the solder matrix creep ductility exhaustion.

Finite Element Modeling Of Dca Assemblies Task 2: Ring Stiffened Dca
Authors: James M. Pitarresi and Dan Fridline
Abstract: This report presents results from the finite element modeling of a ring stiffened, non-underfilled DCA package on a 2.5 mil flex substrate. The focus of the modeling was on the low-cycle, thermal cycling fatigue of the solder joints. The thermal profile used in all simulations was a twenty-minute cycle, 0C to +100C, with five minute ramp and dwell times. The methodology used for predicting the mean joint life was based on the solder’s matrix creep ductility exhaustion. Computation of the component life was based on an assumed Weibull slope and a three-parameter Weibull failure distribution. Computer simulations were done with various package design parameters, including: die size, die thickness, substrate CTE, substrate modulus, substrate thickness, and stiffener thickness. Of these, the component life was most sensitive to the substrate CTE (decreasing life with increasing CTE) and substrate thickness (increasing life with increasing thickness). The component life was insensitive to the ring stiffener thickness over a wide range of values. However, above a critical thickness the component life was sharply reduced.

Finite Element Modeling Of Dca Assemblies Task 3: Solder Joint Fatigue In Underfilled Dca
Authors: James M. Pitarresi and Dan Fridline
Abstract: This report presents results from the finite element modeling of an underfilled DCA package mounted on a 62 mil thick FR-4 substrate. The focus of the modeling was on the low-cycle, thermal cycling fatigue of the solder joints. The thermal profile used in all the computer simulations was a twenty-minute cycle, 0C to +100C, with five minute ramp and dwell times. The methodology used for predicting the mean electrical joint life was based on the tin-lead eutectic solder’s matrix creep ductility exhaustion. Computation of the component life was based on an assumed Weibull slope and a three-parameter Weibull failure distribution. Computer simulations were done with various package design parameters, including: die size, die standoff height, underfill CTE, underfill modulus, underfill fillet length, and distance from die edge to nearest solder joint. The simulations predict that increasing either the die standoff height, underfill CTE, or the underfill modulus will lead to an increase in the component life. An increase in die size reduced the package life. Having the underfill fillet longer (i.e., spread further out from the die) than the height to the top of the die decreased the component life; the best fillet length is one whose length is approximately the same as the height to the top of the die. The simulations predict that moving the joints closer to the die edge (from 9 mils to 4 mils) significantly increased the package life.

Finite Element Modeling Of Dca Assemblies Task 4: Underfill Interface Stresses
Authors: James M. Pitarresi and Dan Fridline
Abstract: This report presents results from the finite element modeling of an underfilled DCA package mounted on a 62 mil thick FR-4 substrate. The focus is on the interface stresses in the underfill. The computer analyses were done with various package design parameters, including: die size, die standoff height, underfill CTE, underfill elastic modulus, underfill fillet length, and distance from die edge to nearest solder joint. The location and magnitude of the maximum interface normal and shear stresses were computed. It was found that the maximum normal and shear interface stresses always occurred under the die, just in from the die edge. The models predict that increasing the die size, underfill CTE, or underfill modulus leads to an increase in the interface stresses. The underfill fillet length and die standoff height had no significant effect on the interface stresses. Changing the distance of the joints from the die edge lead to mixed results: the shear stress decreased when the distance was increased but the normal stress was not significantly affected.

Finite Element Modeling Of Dca Underfill
Authors: James M. Pitarresi and Jeffrey C. Riebling
Abstract: The scope of this report covers the use of the finite element method to estimate the effect that the underfill (also referred to as encapsulant) fillet shape and coefficient of thermal expansion have on the relative solder joint displacements and solder joint stresses. In addition, the stresses at the fillet/chip interface were investigated. The FE model assumed plane stress conditions and linear material response. Six configurations involving changing the geometry of the encapsulant were considered. By applying a one degree temperature change to the model the stresses and displacements were determined. Based upon the results of these models some initial design guidelines were developed concerning the encapsulation of a chip.

The Influence Of Various Mechanical Properties On The Thermally Induced Stress Fields In Dca Assemblies
Authors: Yan Sha, C. Y. Hui and E. J. Kramer
Abstract: Generic DCA assemblies were simulated using a simple two dimensional finite element analysis and assuming good encapsulant adhesion everywhere. Thermal mismatch induced delamination should not be sensitive to encapsulant modulus or assembly standoff on regular FR-4 boards. The encapsulant CTE should, however, be matched to that of the solder. Not surprisingly, a small CTE and thickness of the board should minimize delamination, but the latter also enhances the risk of die cracking. It is emphasized that the presence of flux residues may affect the predicted dependencies.

Underfill Delamination Trends In Dca Assemblies
Authors: Yan Sha, C. Y. Hui and E. J. Kramer
Abstract: Delamination of the underfill is usually the rate limiting step in thermal mismatch induced failure of DCA assemblies. This report explains recent experimental results on this phenomenon including effects of flux residues, on the basis of finite element analysis and a discussion of predicted stress field singularities. The role of the underfill fillet in reducing stress concentrations near the edges of the chip is investigated. The predicted results include an experimentally observed tendency for delamination to start at the solder joints and progress along the passivation surface towards the chip center, rather than towards the outer edges, during thermal cycling. The solder joints should be able to maintain electrical continuity in spite of such delamination, as long as the underfill fillets remain intact. This is also in agreement with observations. The analysis suggests that good adhesion between underfill and solder joints might help compensate for the relatively poor adhesion endemic to epoxy-polyimide interfaces. It also suggests that voids in the underfill material may sometimes be detrimental.

Mechanical Testing Of Flip Chip Underfill Adhesion
Authors: Yan Sha, C. Y. Hui and E. J. Kramer
Abstract: An asymmetric double cantilever beam (ADCB) method is used to measure the interface adhesion of polyimide and underfill in terms of fracture toughness. Due to the big difference in thermal expansion coefficients, a new term in the energy release rate calculation due to thermal residual stresses should be included.

Encapsulant-Flux Interactions
Authors: Jacek Knop and K. Srihari
Abstract: Flux residues are known to affect encapsulant adhesion during thermal excursions. Also, out gassing from residues during encapsulant cure may cause bubbling and void formation. Residue formation and out gassing was investigated by thermogravimetric analysis and differential scanning calorimetry. Melting and redistribution of residues during encapsulant cure was studied in model experiments.

Use Of No Residue Flux For Dca Assemblies
Authors: Jacek Knop and K. Srihari
Abstract: A comparison study of no residue fluxes and commercially available fluxes was made. The experimentation included the use of thermal analysis techniques such as the thermogravimetric analyzer and the differential scanning calorimeter. We also incorporated the use of the wetting balance in order to compare the solderability of the no residue fluxes and the commercially available fluxes. This examination also included the use of the no residue fluxes in real live assemblies which were put through the thermal shock test. We found that the no residue fluxes did perform much better in the wetting balance than the commercially available fluxes. We also found that during thermal shock tests the builds with the no residue fluxes had more delamination compared to the commercially available fluxes.

Initial Screening Of Fluxes For Dca In Terms Of Solderability And Effect On Underfill Adhesion
Authors: Pitchika Ravi Shankar, Sarathy Rajagopalan and K. Srihari
Abstract: The purpose of this research was to evaluate various experimental and commercial fluxes with respect to solderability and effect on underfill adhesion. The fluxes were first tested for their performance when applied on the drum fluxer and/or by dispensing. Some of them were further investigated for their effect on underfill adhesion. Based on this, a set of promising fluxes were selected for further investigation.

Comparison Of A Few Fluxes In Terms Of The Effect On Underfill Adhesion
Authors: Pitchika Ravi Shankar and K. Srihari
Abstract: Screening of a large number of commercial and experimental fluxes in terms of solderability and effect on underfill adhesion led to the identification of two commercial and four epoxy based experimental fluxes for further investigation. The present study used a statistically significant sample size to further test each of these in terms of thermal shock resistance. The Heraeus SF37 and the Kester 244, KK 4-21-1, KK 4-21-3, KK 4-21-4, and KK 4-5-4 were used to attach the nitride passivated Bosch CG555 and CG560 die to .062″ thick FR-4 boards with a Taiyo solder mask. The assemblies were underfilled with the FP4511 encapsulant from Hysol and exposed to Liquid-to-Liquid Thermal Shock. The R244, KK 4-21-3, KK 4-21-4 and KK 4-5-4 fluxes all gave less than 5% delamination during 1500 cycles.

The Impact Of Different Material Combinations On Package Reliability For A Northern Telecom Assembly
Authors: Chien-Yi Huang and K. Srihari
Abstract: The purpose of this study was to research the impact of different materials on package reliability. The flip chip devices used in this study had two different passivation layers, namely SiO2 and polyimide. Three types of fluxes were used and the assembled packages were encapsulated using three different underfill materials. These assembled packages were then subjected to ‘liquid to liquid thermal shock’ testing. The degree of delamination and the percentage of electrical failures were used to indicate the reliability of the packages. This criteria helped to evaluate the performance of the materials used for the assembly and the underfill of the direct chip attach devices. The causes for the failure of these direct chip attach assemblies were identified and discussed. The influence of different materials on package reliability was evaluated. The combination of materials which would result in the least degree of delamination and electrical failure was also identified.

The Impact Of Different Material Combinations On Package Reliability For A Northern Telecom Assembly – An

Authors: Chien-Yi Huang and K. Srihari
Abstract: Selective material combinations used in the experiments addressed in the previous part of the report were subjected to Air to Air Thermal Shock testing (AATS) at Northern Telecom to test for delamination. The conditions used included temperatures of -55C and 125C (same as in LLTS) with ten minutes of dwell time at these temperatures.

Direct Measurement Of The Adhesion Between Polymide And Underfill
Author: JinBao Jiao
Abstract: The interfacial fracture toughness Gc between polyimide and underfill was measured using an asymmetric double cantilever beam (ADCB) sample technique by slowly driving a moving razor blade along the interface. A thin layer of polyimide was coated on a standard diglycidyl ether of bisphenol-A (DGEBA) epoxy plate as one of the beams and an underfill epoxy was molded on the polyimide film as the second beam. Our results demonstrated that the mismatch of the thermal expansion of the DGEBA epoxy and the underfill generates an extra strain energy release rate GT. The release of the thermal stress during the crack propagation along the interface causes the measured Gc to be less than the critical strain energy release rate Gc* that drives the crack along the interface in the absence of thermal stress. Details of the influence of the thermal residual stress on the interfacial fracture toughness have been experimentally investigated. The fracture toughness Gc* of the underfill/polyimide interface is obtained by adding GT to the mechanically measured fracture toughness Gc. The technique enables us to compare quantitatively the Gc*s of different combinations of commercial polyimides with underfills. We also examined the effects on Gc* of the underfill flow temperature and curing conditions of the underfill as well as the polyimide heat treatment.

Thermal Shock Testing Of Dca Assemblies With Problematic Solder Mask
Authors: Ravi Shankar Pitchika, Udayabhaskar Putcha and K. Srihari
Abstract: The initial goal of this research was to study the impact of a variety of process and material parameters on the reliability of several different direct chip attach assemblies. This carefully designed experimental matrix was to have identified the ‘best’ process and material combination(s). Five different types of die were considered in this experiment. However, the massive delamination that was seen (in most cases) early in liquid-to-liquid thermal shock testing (or LLTS) and the corresponding occurrence of electrical failures indicated the presence of a major unknown variable. This was later identified as the inability of most encapsulants to adequately adhere to the solder mask used. Consequently, the goals of this set of experiments had to be significantly curtailed.

Within the reduced scope of this experimental effort, it was still possible to make a few inferences. It was observed that all but one encapsulant (from Zymet) often did not adhere very well to the solder mask surface. The impact of two different pad metallurgies (organic solder protect coated copper and Ni/Au) on assembly reliability was studied, but definite conclusions could not be made. However, baking the assemblies prior to underfill definitely enhanced assembly reliability.

Reliability Testing And Analysis Of Dca Assemblies
Authors: Udayabhaskar Putcha and K. Srihari
Abstract: Reliability of a Direct Chip Attach (DCA) assembly depends on a wide range of factors which include the die passivation, encapsulant, flux, pad metallurgy, board thickness, and soldermask. The present research effort is designed to investigate and identify the effect of different material parameter combinations on the reliability of DCA assemblies. The experimentation follows previous efforts which were discontinued due to a bad soldermask. The test vehicles used in the present experiments were plasma-cleaned to avoid any more problems with the soldermask.

Following elaborate studies on the process and material parameters affecting DCA assemblies, further investigations were carried out to identify main parameters and their interactions. Many assemblies were built with different parameter combinations according to an experimental matrix. All the assemblies were subjected to Liquid-to-Liquid Thermal Shock (LLTS) and their behavior was periodically monitored. Design of experiments and statistical concepts were used as a basis for the experimentation and the analysis of the data. The encapsulant, pad, flux, board thickness, and two-way interaction between flux and pad were found to be the most significant factors. The die passivation type also appeared to influence the DCA package reliability. The electrical behavior of DCA components seemed to depend not only on the extent of delamination, but several other factors.